參數(shù)資料
型號(hào)： MSC8101M1250C
廠商： MOTOROLA INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Network Digital Signal Processor
中文描述： 64-BIT, 62.5 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁(yè)數(shù)： 61/104頁(yè)
文件大?。?/td> 877K
代理商： MSC8101M1250C
AC Timings
MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
2-21
2.6.6
CPM Timings
Table 2-20.
CPM Input Characteristics
No.
Characteristic
Typical
Unit
39
FCC input set-up time before low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial clock input)
10
5
ns
ns
17
FCC input hold time after low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial clock input)
0
3
ns
ns
18
SCC/SMC/SPI/I
2
C input set-up time before low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial clock input)
20
5
ns
ns
19
SCC/SMC/SPI/I
2
C input hold time after low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial clock input)
0
5
ns
ns
20
TDM input set-up time before low-to-high serial clock transition
5
ns
21
TDM input hold time after low-to-high serial transition
5
ns
22
PIO/TIMER/DMA input set-up time before low-to-high serial clock transition
10
ns
23
PIO/TIMER/DMA input hold time after low-to-high serial clock transition
3
ns
Note:
FCC, SCC, SMC, SPI, I
2
C are Non-Multiplexed Serial Interface signals.
Table 2-21.
CPM Output Characteristics
No.
Characteristic
Min
Max
Unit
41
FCC output delay after low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial input clock)
0
2
6
18
ns
ns
38
SCC/SMC/SPI/I
2
C output delay after low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial input clock)
0
0
20
30
ns
ns
40
TDM output delay after low-to-high serial clock transition
5
15
ns
42
PIO/TIMER/DMA output delay after low-to-high serial clock transition
1
14
ns
Note:
FCC, SCC, SMC, SPI, I
2
C are non-multiplexed serial interface signals.
Figure 2-14.
FCC Internal Clock Diagram
BRGxO
FCC inputs
FCC outputs
29a
17a
41a
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