參數(shù)資料
型號(hào)： MSC8101M1250C
廠商： MOTOROLA INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Network Digital Signal Processor
中文描述： 64-BIT, 62.5 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁數(shù)： 40/104頁
文件大小： 877K
代理商： MSC8101M1250C
MSC8101 Technical Data, Rev. 16
1-36
Freescale Semiconductor
Signals/Connections
1.7 JTAG Test Access Port Signals
The MSC8101 supports the standard set of Test Access Port (TAP) signals defined by IEEE 1149.1 Standard Test
Access Port and Boundary-Scan Architecture specification and described in
Table 1-11
.
1.8 Reserved Signals
Table 1-11.
JTAG Test Access Port Signals
Signal Name
Type
Signal Description
TCK
Input
Test Clock
A test clock signal for synchronizing JTAG test logic.
Test Data Input
A test data serial signal for test instructions and data. TDI is sampled on the rising edge of TCK and
has an internal pull-up resistor.
Test Data Output
A test data serial signal for test instructions and data. TDO can be tri-stated. The signal is actively
driven in the shift-IR and shift-DR controller states and changes on the falling edge of TCK.
Test Mode Select
Sequences the test controller’s state machine, is sampled on the rising edge of TCK, and has an
internal pull-up resistor.
Test Reset
Asynchronously initializes the test controller, has an internal pull-up resistor, and must be asserted
after power up.
TDI
Input
TDO
Output
TMS
Input
TRST
Input
Table 1-12.
Reserved Signals
Signal Name
Type
Signal Description
TEST
Input
Test
Used for manufacturing testing. You must connect this input to GND.
Leave disconnected.
Spare Pins
Leave disconnected for backward compatibility with future revisions of this device.
THERM[1–2]
SPARE1, 5
—
—
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