參數(shù)資料
型號： MSC8101M1250C
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： Network Digital Signal Processor
中文描述： 64-BIT, 62.5 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁數(shù)： 56/104頁
文件大?。?/td> 877K
代理商： MSC8101M1250C
MSC8101 Technical Data, Rev. 16
2-16
Freescale Semiconductor
Physical and Electrical Specifications
2.6.4.2 DMA Data Transfers
Table 2-18
describes the DMA signal timing.
The DREQ
signal is synchronized with the falling edge of
DLLIN
.
DONE
timing is relative to the rising edge of
DLLIN
.
To achieve fast response, a synchronized peripheral should assert
DREQ
according to the timings in
Table 2-18
.
Figure 2-7
shows synchronous peripheral interaction.
2.6.5
HDI16 Signals
Table 2-18.
DMA Signals
Number
Characteristic
Minimum
Maximum
Units
72
DREQ set-up time before DLLIN falling edge
6
—
ns
73
DREQ hold time after DLLIN falling edge
0.5
—
ns
74
DONE set-up time before DLLIN rising edge
9
—
ns
75
DONE hold time after DLLIN rising edge
0.5
—
ns
76
DACK/DRACK/DONE delay after DLLIN rising edge
0.5
9
ns
Figure 2-7.
DMA Signals
Table 2-19.
Host Interface (HDI16) Timing
1, 2
Number
Characteristics
3
Expression
Value
Unit
44a
Read data strobe minimum assertion width
4
HACK read minimum assertion width
Read data strobe minimum deassertion width
4
HACK read minimum deassertion width
Read data strobe minimum deassertion width
4
after “Last Data Register”
reads
5,6
, or between two consecutive CVR, ICR, or ISR reads
7
HACK minimum deassertion width after “Last Data Register” reads
5,6
Write data strobe minimum assertion width
8
HACK write minimum assertion width
Write data strobe minimum deassertion width
8
HACK write minimum deassertion width after ICR, CVR and Data Register
writes
5
Host data input minimum set-up time before write data strobe deassertion
8
Host data input minimum set-up time before HACK write deassertion
(1.5
×
T
C
) + 5.0
Note 11
ns
44b
T
C
+ 5.0
Note 11
ns
44c
(2.5
×
T
C
) + 5.0
Note 11
ns
45
(1.5
×
T
C
) + 5.0
Note 11
ns
46
(2.5
×
T
C
) + 5.0
Note 11
ns
47
—
5.0
ns
DLLIN
DREQ
DONE Input
DACK/DONE/DRACK Outputs
73
72
74
75
76
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