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| 型號： | MSC8101M1250C |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Network Digital Signal Processor |
| 中文描述： | 64-BIT, 62.5 MHz, OTHER DSP, PBGA332 |
| 封裝： | 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332 |
| 文件頁數(shù)： | 51/104頁 |
| 文件大?。?/td> | 877K |
| 代理商： | MSC8101M1250C |
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AC Timings
MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
2-11
2.6.3.4 Hardware Reset Configuration
Hardware reset configuration is enabled if
HPE
is sampled low at the rising edge of
PORESET
. The value driven on
RSTCONF
while
PORESET
changes from assertion to deassertion determines the MSC8101 configuration. If
RSTCONF
is deasserted (driven high) while
PORESET
changes, the MSC8101 acts as a configuration slave. If
RSTCONF
is asserted (driven low) while
PORESET
changes, the MSC8101 acts as a configuration master.
Section
2.6.3.4
,
Hardware Reset Configuration
, explains the configuration sequence and the terms “configuration master”
and “configuration slave.”
Directly after the deassertion of
PORESET
and choice of the reset operation mode as configuration master or
configuration slave, the MSC8101 starts the configuration process. The MSC8101 asserts
HRESET
and
SRESET
throughout the power-on reset process, including configuration. Configuration takes 1024
CLOCKIN
cycles, after
which
MODCK[1–3]
are sampled to determine the MSC8101’s working mode.
Next, the MSC8101 halts until the SPLL locks. The SPLL locks according to
MODCK[1–3]
, which are sampled, and
to MODCK_H taken from the Reset Configuration Word. SPLL locking time is 800 reference clocks, which is the
clock at the output of the SPLL Pre-divider. After the SPLL is locked, all the clocks to the MSC8101 are enabled.
If the DLLDIS bit in the reset configuration word is reset, the DLL starts the locking process after the SPLL is
locked. During PLL and DLL locking,
HRESET
and
SRESET
are asserted.
HRESET
remains asserted for another 512
BUS clocks and is then released. The
SRESET
is released three bus clocks later. If the DLLDIS bit in the reset
configuration word is set, the DLL is bypassed and there is no locking process, thus saving the DLL locking time.
Figure 2-4
shows the power-on reset flow.
Figure 2-4.
Hardware Reset Configuration Timing
PORESET
PORESET
Internal
HRESET
Output (I/O)
Input
SRESET
Output (I/O)
RSTCONF is sampled for
master/slave determination
MODCK[1–3] are sampled.
MODCK_H bits are ready
for PLL.
HRESET/SRESET are
extended for 512/515 bus
clocks, respectively, from PLL
and DLL Lock time.
In reset configuration mode:
reset configuration sequence
occurs in this period.
PLL locks after
800 SPLLMFCLKs. DLL
locks 3073 bus clocks after
PLL is locked.
When DLL is disabled, reset
period is shortened by 3073
bus clocks.
1
asserted for
min 16
CLKIN.
2
3
4
PLL locked
DLL locked
5
6
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MSC8101M1250F | 功能描述:DSP 16BIT 250MHZ CPM 332-FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8101M1375C | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Network Digital Signal Processor |
| MSC8101M1375F | 功能描述:DSP 16BIT 275MHZ CPM 332-FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8101M1500F | 功能描述:DSP 16BIT 300MHZ CPM 332-FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8101UG/D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor |
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