參數(shù)資料
型號(hào): MSC8101M1250C
廠商: MOTOROLA INC
元件分類: 數(shù)字信號(hào)處理
英文描述: Network Digital Signal Processor
中文描述: 64-BIT, 62.5 MHz, OTHER DSP, PBGA332
封裝: 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁(yè)數(shù): 6/104頁(yè)
文件大?。?/td> 877K
代理商: MSC8101M1250C
MSC8101 Technical Data, Rev. 16
1-2
Freescale Semiconductor
Signals/Connections
P
O
W
E
R
6
0
x
B
U
S
32
5
4
1
1
3
1
1
1
1
1
1
1
1
32
A[0–31]
TT[0–4]
TSIZ[0–3]
TBST
IRQ1
Reserved
BR
BG
ABB
TS
AACK
ARTRY
DBG
DBB
D[0–31]
VDD
VDDH
VCCSYN
VCCSYN1
14
25
1
1
GBL
BADDR[29–31]
IRQ[2–3, 5]
GND
37
1
1
GNDSYN
GNDSYN1
IRQ2
C
P
M
I
/
O
P
O
R
T
S
For the signals
multiplexed on
Ports A–D,
see
Figure 1-2
Port A
PA[31–6]
26
IRQ3
Port B
HDI16 Signals
PB[31–18]
14
16
4
1
D[32–47]
D[48–51]
D52
HD[0–15]
HA[0–3]
HCS1
Single DS
HRW
HDS/HDS
Single HR
HREQ/HREQ
HACK/HACK
HDSP
HDDS
H8BIT
HCS2
Reserved
Port C
PC[31–22, 15–12, 7–4]
18
Double DS
HRD/HRD
HWR/HWR
Double HR
HTRQ/HTRQ
HRRQ/HRRQ
1
1
D53
D54
Port D
PD[31–29, 19–16, 7]
8
1
1
1
1
1
1
4
D55
D56
D57
D58
D59
D60
D[61–63]
J
T
A
G
TMS
TDI
TCK
TRST
TDO
1
1
1
1
1
1
Reserved
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
TA
TEA
NMI
NMI_OUT
PSDVAL
IRQ7
DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
Reserved
IRQ1
Reserved
Reserved
DREQ3
DREQ4
DACK3
DACK4
EXT_Br2
EXT_BG2
EXT_DBG2
EXT_BR3
EXT_BG3
EXT_DBG3
IRQ6
IRQ7
EOnCE Event
RESET
Configuration
1
EED
EE0
EE1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DBREQ
HPE
EE[2–3]
EE[4–5]
BTM[0–1]
PORESET
RSTCONF
HRESET
SRESET
INT_OUT
M
E
M
C
8
1
CS[0–7]
BCTL1
BADDR[27–28]
ALE
BCTL0
PWE[0–7]
PSDA10
PSDWE
POE
PSDCAS
PGTA
PSDAMUX
CLKIN
1
BNK-
SEL[0–2]
TC[0–2]
MODCK[1–3]
CLKOUT
3
2
1
1
1
1
8
1
1
1
1
1
1
DLLIN
PSDDQM[0–7]
PBS[0–7]
PGPL0
PGPL1
PGPL2
PGPL3
PGPL4
PGPL5
PSDRAS
TEST
1
2
2
THERM[1–2]
SPARE1
,
SPARE5
PUPMWAIT
PPBS
Note:
Refer to the
System Interface Unit (SIU)
chapter in the
MSC8101 Reference Manual
for details on how to configure these pins.
Figure 1-1.
MSC8101 External Signals
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