參數(shù)資料
型號： MSC8101M1250C
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： Network Digital Signal Processor
中文描述： 64-BIT, 62.5 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁數(shù)： 28/104頁
文件大小： 877K
代理商： MSC8101M1250C
MSC8101 Technical Data, Rev. 16
1-24
Freescale Semiconductor
Signals/Connections
1.6.3
Port C Signals
PB18
FCC2: RXD3
MII
and
HDLC nibble
I
2
C: SCL
Input
Input/Output
FCC2: MII and HDLC Nibble Receive Data Bit 3
RXD3 is bit 3 and the most significant bit of the receive data nibble.
I
2
C: Inter-Integrated Circuit Serial Clock
The I
2
C interface comprises two signals: serial data (SDA) and serial
clock (SDA). The I
2
C controller uses a synchronous, multimaster bus
that can connect several integrated circuits on a board. Clock rates run
up to 520 kHz@25 MHz system clock.
Table 1-9.
Port C Signals
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated I/O
Protocol
PC31
BRG1O
CLK1
TIMER1/2: TGATE1
Output
Input
Input
Baud-Rate Generator 1 Output
The CPM supports up to 8 BRGs used internally by the bank-of-clocks
selection logic and/or to provide an output to one of the 8 BRG pins.
BRG1O can be the internal input to the SIU timers. When CLK5 is selected
(see PC27 below), it is the source for BRG1O which is the default input for
the SIU timers. See the system interface unit (SIU) chapter in the
MSC8101 Reference
Manual
for additional information. If CLK5 is not
enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26
below), the BRG1O input to the SIU timers is disabled.
Clock 1
The CPM supports up to 10 clock input pins sent to the bank-of-clocks
selection logic, where they can be routed to the controllers.
Timer 1/2: Timer Gate 1
The timers can be gated/restarted by an external gate signal. There are
two gate signals: TGATE1 controls timer 1 and/or 2 and TGATE2 controls
timer 3 and/or 4.
Table 1-8.
Port B Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated I/O
Protocol
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相關代理商/技術參數(shù)
參數(shù)描述
MSC8101M1250F 功能描述:DSP 16BIT 250MHZ CPM 332-FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
MSC8101M1375C 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Network Digital Signal Processor
MSC8101M1375F 功能描述:DSP 16BIT 275MHZ CPM 332-FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
MSC8101M1500F 功能描述:DSP 16BIT 300MHZ CPM 332-FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
MSC8101UG/D 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor
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