參數(shù)資料
型號(hào)： MSC8101M1250C
廠商： MOTOROLA INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： Network Digital Signal Processor
中文描述： 64-BIT, 62.5 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁(yè)數(shù)： 23/104頁(yè)
文件大?。?/td> 877K
代理商： MSC8101M1250C
CPM Ports
MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
1-19
PA17
FCC1: RXD7
UTOPIA
FCC1: RXD0
MII
and
HDLC nibble
FCC1: RXD
HDLC serial
and
transparent
Input
Input
Input
FCC1: UTOPIA Receive Data Bit 7.
The MSC8101 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. RXD7 is the most significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY
configurations, RXD[0–7] is tri-stated, enabled only when RXENB is
asserted.
FCC1: MII and HDLC Nibble Receive Data Bit 0
RXD[3–0] is supported by MII and HDLC nibble mode in FCC1. RXD0 is
the least significant bit.
FCC1: HDLC Serial and Transparent Receive Data Bit
This is the single receive data bit supported by HDLC and transparent
modes.
PA16
FCC1: RXD6
UTOPIA
FCC1: RXD1
MII
and
HDLC nibble
Input
Input
FCC1: UTOPIA Receive Data Bit 6.
The MSC8101 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. This is bit 6 of the receive data. RXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated,
enabled only when RXENB is asserted.
FCC1: MII and HDLC Nibble Receive Data Bit 1
This is bit 1 of the receive nibble data. RXD3 is the most significant bit.
PA15
FCC1: RXD5
UTOPIA
RXD2
MII
and
HDLC nibble
Input
Input
FCC1: UTOPIA Receive Data Bit 5
The MSC8101 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. This is bit 5 of the receive data. RXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated,
enabled only when RXENB is asserted.
FCC1: MII and HDLC Nibble Receive Data Bit 2
This is bit 2 of the receive nibble data. RXD3 is the most significant bit.
PA14
FCC1: RXD4
UTOPIA
FCC1: RXD3
MII
and
HDLC nibble
Input
Input
FCC1: UTOPIA Receive Data Bit 4.
The MSC8101 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated,
enabled only when RXENB is asserted.
FCC1: MII and HDLC Nibble Receive Data Bit 3
RXD3 is the most significant bit of the receive nibble bit.
PA13
FCC1: RXD3
UTOPIA
SDMA: MSNUM2
Input
Output
FCC1: UTOPIA Receive Data Bit 3
The MSC8101 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least significant
bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is
tri-stated, enabled only when RXENB is asserted.
Module Serial Number Bit 2
The MSNUM has 6 bits that identify devices using the serial DMA
(SDMA) modules. MSNUM[0–4] is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates the section,
transmit (0) or receive (1), that is active during the transfer. The
information is recorded in the SDMA transfer error registers.
Table 1-7.
Port A Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated Signal
Protocol
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MSC8101M1250F 功能描述:DSP 16BIT 250MHZ CPM 332-FCPBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類(lèi)型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類(lèi)型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤(pán) 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
MSC8101M1375C 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:Network Digital Signal Processor
MSC8101M1375F 功能描述:DSP 16BIT 275MHZ CPM 332-FCPBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類(lèi)型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類(lèi)型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤(pán) 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
MSC8101M1500F 功能描述:DSP 16BIT 300MHZ CPM 332-FCPBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類(lèi)型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類(lèi)型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤(pán) 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
MSC8101UG/D 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor
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