參數(shù)資料
型號(hào)： MPC8245TZU333D
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 333 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352
文件頁(yè)數(shù)： 58/60頁(yè)
文件大?。?/td> 674K
代理商： MPC8245TZU333D
MOTOROLA
MPC8245 Integrated Processor Hardware Specications
7
Electrical and Thermal Characteristics
1.4.1.2
Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8245.
Table 2. Recommended Operating Conditions
Characteristic
Symbol
Recommended
Value
Unit
Notes
Supply voltage
VDD
1.8 ± 100 mV
V
4, 6
2.0 ± 100 mV
V
6
I/O buffer supply for PCI and standard
OVDD
3.3 ± 0.3
V
6
Supply voltages for memory bus drivers
GVDD
3.3 ± 5%
V
8
CPU PLL supply voltage
AVDD
1.8 ± 100 mV
V
4, 6
2.0 ± 100 mV
V
6
PLL supply voltage—peripheral logic
AVDD2
1.8 ± 100 mV
V
4, 6
2.0 ± 100 mV
V
6
PCI reference
LVDD
5.0 ± 5%
V
2, 9, 10
3.3 ± 0.3
V
3, 9, 10
Input voltage
PCI inputs
Vin
0 to 3.6 or 5.75
V
2, 3
All other inputs
0 to 3.6
V
5
Die-junction temperature
Tj
0 to 105
°C
Notes:
1.
These are the recommended and tested operating conditions. Proper device operation outside of these conditions
is not guaranteed.
2.
PCI pins are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 5.0 V DC power supply.
3.
PCI pins are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 3.3 V DC power supply.
4.
CPU speed limited to 266 and 300 MHz operation at this voltage. See Table 7.
Cautions:
5.
Input voltage (Vin) must not be greater than the supply voltage (VDD/AVDD/AVDD2) by more than 2.5 V at all times
including during power-on reset. Input voltage (Vin) must not be greater than GVDD/OVDD by more than 0.6 V at
all times including during power-on reset.
6.
OVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8 V at any time including during power-on reset.This limit
may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
7.
VDD/AVDD/AVDD2 must not exceed OVDD by more than 0.6 V at any time including during power-on reset. This
limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
8.
GVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8 V at any time including during power-on reset. This
limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
9.
LVDD must not exceed VDD/AVDD/AVDD2 by more than 5.4 V at any time including during power-on reset. This limit
may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
10. LVDD must not exceed OVDD by more than 3.0 V at any time including during power-on reset. This limit may be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
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