參數(shù)資料
型號： MPC8245TZU333D
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 333 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352
文件頁數(shù)： 5/60頁
文件大?。?/td> 674K
代理商： MPC8245TZU333D
MOTOROLA
MPC8245 Integrated Processor Hardware Specications
13
Electrical and Thermal Characteristics
1.4.3.1
Clock AC Specications
Table 8 provides the clock AC timing specications at recommended operating conditions, as dened in
Section 1.4.3.2, “Input AC Timing Specications.” These specications are for the default driver strengths
indicated in Table 4. Figure 4 shows the PCI_SYNC_IN input clock timing diagram with the labeled
number items listed in Table 8.
Table 7. Operating Frequency 1
Characteristic 2, 3
266 MHz
300 MHz
333 MHz
350 MHz
Unit
VDD/AVDD/AVDD2 = 1.8/2.0 ± 100 mV
VDD/AVDD/AVDD2 = 2.0 ± 100 mV
Processor frequency
(CPU)
100–266
100–300
100–333
100–350
MHz
Memory bus frequency
50–133
50–100 4
50–133
50–100 4
MHz
PCI input frequency
25–66
MHz
Notes:
1. See part number specication document MPC8245RZUPNS/D for additional part offering information.
2. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the resulting
peripheral logic/memory bus frequency and CPU (core) frequencies do not exceed their respective maximum or
minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 1.6, “PLL Conguration,”
for valid PLL_CFG[0:4] settings and PCI_SYNC_IN frequencies.
3. See Table 18 and Table 19 for more details on VCO limitations for memory and CPU VCO frequencies of various
PLL congurations.
4. There are no available PLL_CFG[0:4] settings which support 133 MHz memory interface operation at 300 MHz
CPU and 350 MHz operation, since the multipliers do not allow a 300:133 and 350:133 ratio relation. However,
running these parts at slower processor speeds may produce ratios that will run above 100 MHz. See Table 18 for
the PLL settings.
Table 8. Clock AC Timing Specications
At recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V
Num
Characteristics and Conditions
Min
Max
Unit
Notes
1a
Frequency of operation (PCI_SYNC_IN)
25
66
MHz
2, 3
PCI_SYNC_IN rise and fall times
—
2.0
ns
1
4
PCI_SYNC_IN duty cycle measured at 1.4 V
40
60
%
5a
PCI_SYNC_IN pulse width high measured at 1.4 V
6
9
ns
2
5b
PCI_SYNC_IN pulse width low measured at 1.4 V
6
9
ns
2
7
PCI_SYNC_IN jitter
—
150
ps
8a
PCI_CLK[0:4] skew (pin-to-pin)
—
250
ps
8b
SDRAM_CLK[0:3] skew (pin-to-pin)
—
190
ps
3
10
Internal PLL relock time
—
100
s
2, 4, 5
15
DLL Lock Range with DLL_EXTEND = 0 disabled
(default)
(N
× Tclk – Tdp(max)) ≤ Tloop
≤ (N × Tclk – Tdp(min))
ns
6
16
DLL lock range with DLL_EXTEND = 1 enabled
((N – 0.5)
× Tclk – Tdp(max)) ≤ Tloop
≤ ((N – 0.5) × Tclk – Tdp(min))
ns
6
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