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參數(shù)資料
| 型號： | MPC8245TZU333D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 333 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352 |
| 文件頁數(shù)： | 38/60頁 |
| 文件大小： | 674K |
| 代理商： | MPC8245TZU333D |
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MOTOROLA
MPC8245 Integrated Processor Hardware Specications
43
System Design Information
1.7
System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8245.
1.7.1
PLL Power Supply Filtering
The AVDD and AVDD2 power signals are provided on the MPC8245 to provide power to the peripheral
logic/memory bus PLL and the MPC603e processor PLL. To ensure stability of the internal clocks, the
power supplied to the AVDD and AVDD2 input signals should be ltered of any noise in the 500 kHz to
10 MHz resonant frequency range of the PLLs. Two separate circuits similar to the one shown in Figure 25
using surface mount capacitors with minimum effective series inductance (ESL) is recommended for AVDD
and AVDD2 power signal pins. Consistent with the recommendations of Dr. Howard Johnson in High Speed
Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value
are recommended over using multiple values.
The circuits should be placed as close as possible to the respective input signal pins to minimize noise
coupled from nearby circuits. Routing directly as possible from the capacitors to the input signal pins with
minimal inductance of vias is important.
Figure 25. PLL Power Supply Filter Circuit
1.7.2
Power Supply Sizing
supplies which are non-negligible for the MPC8245. In typical application measurements, the OVDD power
ranged from 200 to 500 mW and the GVDD power ranged from 300 to 600 mW. The ranges’ low-end power
numbers were results of the MPC8245 performing cache resident integer operations at the slowest
frequency combination of 33:66:200 (PCI:Mem:CPU) MHz. The OVDD high end range’s value resulted
from the MPC8245 operating at the fastest frequency combination of 66:100:350 (PCI:Mem:CPU) MHz
and performing continuous ushes of cache lines with alternating ones and zeros to PCI memory. The GVDD
high-end range’s value resulted from the MPC8245 operating at the fastest frequency combination of
66:100:350 (PCI:Mem:CPU) MHz and performing continuous ushes of cache lines with alternating ones
and zeros on 64-bit boundaries to local memory.
1.7.3
Decoupling Recommendations
Due to its dynamic power management feature, the large address and data buses, and its high operating
frequencies, the MPC8245 can generate transient power surges and high frequency noise in its power
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC8245 system, and the MPC8245 itself requires a clean, tightly regulated source of
power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each
VDD, OVDD, GVDD, and LVDD pin of the MPC8245. It is also recommended that these decoupling
capacitors receive their power from dedicated power planes in the PCB, utilizing short traces to minimize
VDD
AVDD or AVDD2
2.2 F
GND
Low ESL Surface Mount Capacitors
10
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