參數(shù)資料
型號: MPC8245TZU333D
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 333 MHz, RISC PROCESSOR, PBGA352
封裝: 35 X 35 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352
文件頁數(shù): 39/60頁
文件大?。?/td> 674K
代理商: MPC8245TZU333D
44
MPC8245 Integrated Processor Hardware Specications
MOTOROLA
System Design Information
inductance. These capacitors should have a value of 0.1 F. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0508 or 0603, oriented such that
connections are made along the length of the part.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
to minimize inductance. Suggested bulk capacitors: 100–330 F (AVX TPS tantalum or Sanyo OSCON).
1.7.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active-low inputs should be tied to OVDD. Unused active-high inputs should be connected to
GND. All NC (no connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, GVDD, LVDD, and GND pins of
the MPC8245.
The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then returned to
the PCI_SYNC_IN input of the MPC8245.
The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then
returned to the SDRAM_SYNC_IN input of the MPC8245. The trace length may be used to skew or adjust
the timing window as needed. See Motorola application notes AN1849/D, MPC107 Design Guide, and
AN2164/D, MPC8245/MPC8241 Memory Clock Design Guidelines, for more information on this topic.
Note that there is an SDRAM_SYNC_IN to PCI_SYNC_IN time requirement (see Table 10).
1.7.5
Pull-Up/Pull-Down Resistor Requirements
The data bus input receivers are normally turned off when no read operation is in progress; therefore, they
do not require pull-up resistors on the bus. The data bus signals are: MDH[0:31], MDL[0:31], and PAR[0:7].
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (MDL[0:31]
and PAR[4:7]) will be disabled, and their outputs will drive logic zeros when they would otherwise normally
be driven. For this mode, these pins do not require pull-up resistors and should be left unconnected by the
system to minimize possible output switching.
The TEST0 pin requires a pull-up resistor of 120
or less connected to OV
DD.
It is recommended that RTC have weak pull-up resistors (2–10 k
) connected to GV
DD.
It is recommended that the following signals be pulled up to OVDD with weak pull-up resistors (2–10 k):
SDA, SCL, SMI, SRESET/SDMA12, TBEN/SDMA13, CHKSTOP_IN/SDMA14, TRIG_IN/RCS2, INTA,
and DRDY
It is recommended that the following PCI control signals be pulled up to LVDD with weak pull-up resistors
(2–10 k
): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, and TRDY. The resistor values may
need to be adjusted stronger to reduce induced noise on specic board designs.
The following pins have internal pull-up resistors enabled at all times: REQ[3:0], REQ4/DA4, TCK, TDI,
TMS, and TRST. See Table 17 for more information.
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