參數(shù)資料
型號(hào): MPC8245TZU333D
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 333 MHz, RISC PROCESSOR, PBGA352
封裝: 35 X 35 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352
文件頁數(shù): 34/60頁
文件大?。?/td> 674K
代理商: MPC8245TZU333D
4
MPC8245 Integrated Processor Hardware Specications
MOTOROLA
Features
– 272 Mbytes of base and extended ROM/Flash/PortX space
– Base ROM space supports 8-bit data path or same size as the SDRAM data path (32- or
64-bit)
– Extended ROM space supports 8-, 16-, 32-bit gathering data path, 32- or 64-bit (wide) data
path
– PortX: 8-, 16-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with
programmable address strobe timing, data ready input signal (DRDY), and 4 chip selects
— 32-bit PCI interface
– Operates up to 66 MHz
– PCI 2.2-compatible
– PCI 5.0-V tolerance
– Support for dual address cycle (DAC) for 64-bit PCI addressing (master only)
– Support for PCI locked accesses to memory
– Support for accesses to PCI memory, I/O, and conguration spaces
– Selectable big- or little-endian operation
– Store gathering of processor-to-PCI write and PCI-to-memory write accesses
– Memory prefetching of PCI read accesses
– Selectable hardware-enforced coherency
– PCI bus arbitration unit (ve request/grant pairs)
– PCI agent mode capability
– Address translation with two inbound and outbound units (ATU)
– Some internal conguration registers accessible from PCI
— Two-channel integrated DMA controller (writes to ROM/PortX not supported)
– Supports direct mode or chaining mode (automatic linking of DMA transfers)
– Supports scatter gathering—read or write discontinuous memory
– 64-byte transfer queue per channel
– Interrupt on completed segment, chain, and error
– Local-to-local memory
– PCI-to-PCI memory
– Local-to-PCI memory
– PCI memory-to-local memory
— Message unit
– Two doorbell registers
– Two inbound and two outbound messaging registers
–I2O message interface
—I2C controller with full master/slave support that accepts broadcast messages
— Programmable interrupt controller (PIC)
– Five hardware interrupts (IRQs) or 16 serial interrupts
– Four programmable timers with cascade
— Two (dual) universal asynchronous receiver/transmitters (UARTs)
— Integrated PCI bus and SDRAM clock generation
— Programmable PCI bus and memory interface output drivers
System level performance monitor facility
相關(guān)PDF資料
PDF描述
MPC8245TVV350D 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352
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