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參數(shù)資料
| 型號： | MPC8245TZU333D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 333 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352 |
| 文件頁數(shù)： | 37/60頁 |
| 文件大?。?/td> | 674K |
| 代理商： | MPC8245TZU333D |
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42
MPC8245 Integrated Processor Hardware Specications
MOTOROLA
PLL Configuration
1C
1110012
446–661
66–99
198–297
446–661
66–99
198–297
1.5 (2)
3 (2)
1D
1110112
486–661
72–99
180–248
486–661
72–99
180–248
1.5 (2)
2.5(2)
1E
111108
Not Usable
Off
1F
111118
Not Usable
Off
Notes:
1.
Limited by maximum PCI input frequency (66 MHz).
2.
Limited by maximum system memory interface operating frequency (100 MHz @ 350 MHz CPU).
3.
Limited by minimum memory VCO frequency (133 MHz).
4.
Limited due to maximum memory VCO frequency (372 MHz).
5.
Limited by maximum CPU operating frequency.
6.
Limited by minimum CPU VCO frequency (360 MHz).
7.
Limited by maximum CPU VCO frequency (800 MHz).
8.
In clock off mode, no clocking occurs inside the MPC8245 regardless of the PCI_SYNC_IN input.
9.
Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.
10. PLL_CFG[0:4] settings not listed are reserved.
11. Multiplier ratios for this PLL_CFG[0:4] setting are different from the MPC8240 and are not backwards-compatible.
12. PCI_SYNC_IN range for this PLL_CFG[0:4] setting is different from the MPC8240 and may not be fully
backwards-compatible.
13. Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.
14. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL
is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware
modeling support. The AC timing specications given in this document do not apply in PLL bypass mode.
15. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the
peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this
mode, the OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and
the processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This
mode is intended for hardware modeling support. The AC timing specications given in this document do not apply
in dual PLL bypass mode.
16. Limited by maximum system memory interface operating frequency (133 MHz @ 333 MHz CPU).
17. Limited by minimum CPU operating frequency (100 MHz).
18. Limited by minimum memory bus frequency (50 MHz).
19. PCI_SYNC_IN range for this PLL_CFG[0:4] setting does not exist on the MPC8240 and may not be fully
backwards-compatible.
20. No longer supported.
Table 19. PLL Congurations (333- and 350-MHz Parts) (continued)
Ref
PLL_
CFG
[0:4] 10,13
333 MHz Part 9
350 MHz Part 9
Multipliers
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/
Mem
Bus
Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/
Mem
Bus
Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI-to-
Mem
(Mem
VCO)
Mem-to-
CPU
(CPU
VCO)
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