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參數(shù)資料
| 型號： | MPC8245TZU333D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 333 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352 |
| 文件頁數(shù)： | 40/60頁 |
| 文件大?。?/td> | 674K |
| 代理商： | MPC8245TZU333D |
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MOTOROLA
MPC8245 Integrated Processor Hardware Specications
45
System Design Information
The following pins have internal pull-up resistors enabled only while device is in the reset state:
GNT4/DA5, MDL0, FOE, RCS0, SDRAS, SDCAS, CKE, AS, MCP, MAA[0:2], PMAA[0:2], and
QACK/DA0. See Table 17 for more information.
The following pins are reset conguration pins: GNT4/DA5, MDL[0], FOE, RCS0, CKE, AS, MCP,
QACK/DA0, MAA[0:2], PMAA[0:2], SDMA[1:0], MDH[16:31], and PLL_CFG[0:4]/DA[10:15]. These
pins are sampled during reset to congure the device. The PLL_CFG[0:4] signals are sampled a few clocks
after the negation of HRST_CPU and HRST_CTRL.
Reset conguration pins should be tied to GND via 1-k
pull-down resistors to ensure a logic zero level is
read into the conguration bits during reset if the default logic-one level is not desired.
Any other unused active low input pins should be tied to a logic-one level via weak pull-up resistors
(2–10 k
) to the appropriate power supply listed in Table 17. Unused active high input pins should be tied
to GND via weak pull-down resistors (2–10 k
).
1.7.6
PCI Reference Voltage—LVDD
The MPC8245 PCI reference voltage (LVDD) pins should be connected to 3.3 ± 0.3 V power supply if
interfacing the MPC8245 into a 3.3-V PCI bus system. Similarly, the LVDD pins should be connected to
5.0 V ± 5% power supply if interfacing the MPC8245 into a 5-V PCI bus system. For either reference
voltage, the MPC8245 always performs 3.3-V signaling as described in the PCI Local Bus Specication
(Rev. 2.2). The MPC8245 tolerates 5-V signals when interfaced into a 5-V PCI bus system.
1.7.7
MPC8245 Compatibility with MPC8240
The MPC8245 AC timing specications are backwards-compatible with those of the MPC8240, except for
the requirements of item 11 in Table 10. Timing adjustments are needed as specied for Tos
(SDRAM_SYNC_IN to sys_logic_clk offset) time requirements.
The MPC8245 does not support the SDRAM ow-through memory interface.
The nominal core VDD power supply changes from 2.5 V on the MPC8240 to 1.8/2.0 V on the MPC8245.
See Table 2 for details.
The MPC8245 PLL_CFG[0:4] setting 0x02 (0b00010) has a different ‘PCI-to-Mem’ and ‘Mem-to-CPU’
multiplier ratio than the same setting on the MPC8240, and thus, is not backwards-compatible. See Table 18
for details.
Most of the MPC8240 PLL_CFG[0:4] settings are subsets of the PCI_SYNC_IN input frequency range
accepted by the MPC8245. However, the parts will not be fully backwards-compatible since the ranges of
the two parts do not always match. Note that modes 0x8 and 0x18 of the MPC8245 are not compatible with
There are two additional reset conguration signals on the MPC8245 which are not used as reset
conguration signals on the MPC8240: SDMA0 and SDMA1.
The SDMA0 reset conguration pin selects between the MPC8245 DUART or the MPC8240 backwards
compatible mode PCI_CLK[0:4] functionality on these multiplexed signals. The default state (logic 1) of
SDMA0 selects the MPC8240 backwards compatible mode of PCI_CLK[0:4] functionality while a logic 0
state on the SDMA0 signal selects DUART functionality. Note if using the DUART mode, four of the ve
PCI clocks, PCI_CLK[0:3], are not available.
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