參數(shù)資料
型號(hào): MMC2001
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 32-BIT, 34 MHz, RISC PROCESSOR, PQFP144
封裝: PLASTIC, TQFP-144
文件頁(yè)數(shù): 233/260頁(yè)
文件大?。?/td> 3848K
代理商: MMC2001
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MMC2001
REFERENCE MANUAL
PROGRAMMING REFERENCE
MOTOROLA
C-37
Every attempt has been made to allow the receiver to correctly interpret data follow-
ing a character marked as having a framing error. (This includes ignoring the start bit
validation logic, if appropriate.) However, when the transmitted data includes two stop
bits, and both stop bits are incorrect, then the second stop bit will be interpreted as
the start bit of the next character.
0 =
Character has no framing error
1 =
Character has a framing error
At reset, this bit is cleared to zero.
BRK — Break Detect
When set, this read-only bit indicates that the current character was detected as a
break. The data bits are all zero and the stop bit is also zero. The frame error bit is
always set when this bit is set. When odd parity is selected, parity error is set when
this bit is set. This bit is valid for each character read from the FIFO.
0 =
Character is not a break character
1 =
Character is a break character
At reset, this bit is cleared to zero.
PRERR — Parity Error
When set, this read-only bit indicates that the current character was detected with a
parity error. The data is possibly corrupted. This bit is updated for each character
read from the FIFO. While parity is disabled, this bit always reads zero.
0 =
No parity error detected for data in RX DATA field
1 =
Parity error detected for data in RX DATA field
At reset, this bit is cleared to zero.
RX DATA — Received Data
These read-only bits are the received character. In 7-bit mode, the MSB is forced to
zero. In 8-bit mode, all bits are active.
C.9.2 UART Transmit Register (UTX)
The UART transmit register is used by the host to write the data to be transmitted.
The low byte is write-only. When this register is read, bits TX[15:8] always return
zero, and TX[7:0] is not driving the bus. The TX register is echoed to 16-word
addresses in order to support filling the transmit FIFO with the store register quadrant
(
stq
) instruction.
*Echoes begin at 10009044 and 1000A044 respectively.
X = Undefined
Figure C-37 UART Transmit Register
U0TX
— UART0 Transmit Register
U1TX
— UART1 Transmit Register
10009040*
1000A040*
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
6
5
4
3
2
1
0
R
W
RESET:
TX DATA
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
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