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| 型號(hào)： | MMC2001 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 32-BIT, 34 MHz, RISC PROCESSOR, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 178/260頁(yè) |
| 文件大小： | 3848K |
| 代理商： | MMC2001 |
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MOTOROLA
16-16
OnCE DEBUG MODULE
MMC2001
REFERENCE MANUAL
When the trace counter decrements to zero, the OnCE control logic requests that the
processor re-enter debug mode, and the trace occurrence bit TO in the OSR is set to
indicate that debug mode has been requested as a result of the trace count function.
The trace counter allows a minimum of two instructions to be specified for execution
prior to entering trace (specified by a count value of one), unless the sequential
breakpoint control capability described in
16.6.2 OnCE Control Register (OCR)
is
being used. In this case a value of zero (indicating a single instruction) is allowed.
16.10 Methods of Entering Debug Mode
The OSR indicates that the CPU has entered debug mode via the PM status field.
The following paragraphs discuss conditions that invoke debug mode.
16.10.1 Debug Request During RESET
When the DR bit in the OCR is set, assertion of RESET causes the device to enter
debug mode. In this case the device may fetch the reset vector and the first instruc-
tion of the reset exception handler but does not execute an instruction before entering
debug mode.
16.10.2 Debug Request During Normal Activity
Setting the DR bit in the OCR during normal device activity causes the device to fin-
ish the execution of the current instruction and then enter debug mode. Note that in
this case the device completes the execution of the current instruction and stops after
the newly fetched instruction enters the CPU instruction latch. This process is the
same for any newly fetched instruction, including instructions fetched by interrupt pro-
cessing or those that will be aborted by interrupt processing.
16.10.3 Debug Request During Stop, Doze, or Wait Mode
Setting the DR bit in the OCR when the device is in stop, doze, or wait mode (i. e.,
has executed a
stop, doze,
or
wait
instruction) causes the device to exit the low-
power state and enter the debug mode. Note that in this case, the device completes
the execution of the
stop, doze,
or
wait
instruction and halts after the next instruction
enters the instruction latch.
16.10.4 Software Request During Normal Activity
Executing the
bkpt
instruction when the FDB (force debug enable mode) control bit in
the control state register is set, causes the CPU to enter debug mode after the
instruction following the
bkpt
instruction has entered the instruction latch.
16.10.5 Enabling OnCE Trace Mode
When the OnCE trace mode mechanism is enabled and the trace count is greater
than zero, the trace counter is decremented for each instruction executed. Complet-
ing execution of an instruction when the trace counter is zero causes the CPU to
enter debug mode.
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