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| 型號(hào)： | MMC2001 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 32-BIT, 34 MHz, RISC PROCESSOR, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 165/260頁(yè) |
| 文件大小： | 3848K |
| 代理商： | MMC2001 |
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MMC2001
REFERENCE MANUAL
OnCE DEBUG MODULE
MOTOROLA
16-3
Resources contained in the OnCE module that do not require the CPU to be halted
for access may be controlled while the CPU is executing and do not interfere with
normal processor execution. Accesses to certain resources, such as the PC FIFO
and the count registers, while not part of the CPU, may require the CPU to be
stopped to allow access to avoid synchronization hazards. If it is known that the CPU
clock is enabled and running no slower than the TCK input, there is sufficient syn-
chronization performed to allow reads but not writes of these specific resources.
Debug firmware may ensure that it is safe to access these resources by reading the
OSR to determine the state of the CPU prior to access. All other cases require the
CPU to be in the debug state for deterministic operation.
16.3 OnCE Pins
The following paragraphs describe the pins associated with the OnCE controller and
serial interface component.
The OnCE pin interface is used to transfer OnCE instructions and data to the OnCE
control block. Depending on the particular resource being accessed, the CPU may
need to be placed in debug mode. For resources outside of the CPU block and con-
tained in the OnCE block, the processor is not disturbed and may continue execution.
If a processor resource is required, the OnCE controller may assert a debug request
(DBGRQ) to the CPU. This causes the CPU to finish the instruction being executed,
save the instruction pipeline information, enter debug mode, and wait for further com-
mands. Asserting DBGRQ causes the device to exit stop, doze, or wait mode.
16.3.1 Debug Serial Input (TDI)
Data and commands are provided to the OnCE controller through the TDI pin. Data is
latched on the rising edge of the TCK serial clock. Data is shifted into the OnCE serial
port least significant bit (LSB) first.
16.3.2 Debug Serial Clock (TCK)
The TCK pin supplies the serial clock to the OnCE control block. The serial clock pro-
vides pulses required to shift data and commands into and out of the OnCE serial
port. (Data is clocked into the OnCE on the rising edge and is clocked out of the
OnCE serial port on the falling edge.) The debug serial clock frequency must be no
greater than 50% of the processor clock frequency.
16.3.3 Debug Serial Output (TDO)
Serial data is read from the OnCE block through the TDO pin. Data is always shifted
out the OnCE serial port LSB first. Data is clocked out of the OnCE serial port on the
falling edge of TCK. TDO is three-stateable and is actively driven in the shift-IR and
shift-DR controller states. TDO changes on the falling edge of TCK.
16.3.4 Debug Mode Select (TMS)
The debug mode select input is used to cycle through states in the OnCE debug con-
troller. Toggling the TMS pin while clocking with TCK controls the transitions through
the TAP state controller.
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