參數(shù)資料
型號(hào)： MMC2080VF001
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： Integrated Processor with Roaming FLEX Decoder
中文描述： 32-BIT, MROM, RISC MICROCONTROLLER, PBGA144
封裝： 12 X 12 MM, 0.80 MM PITCH, MOLD ARRAY PROCESS, BGA-144
文件頁(yè)數(shù)： 1/34頁(yè)
文件大?。?/td> 768K
代理商： MMC2080VF001
MMC2080/2075/D
Rev. 0
,
10/1999
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
Motorola, Inc., 1999. All rights reserved.
Semiconductor Products Sector
MMC2080/2075
Advance Information
MMC2080/2075 Integrated Processor with
Roaming FLEX Decoder
Part 1 Introduction
The MMC2080/2075 is designed to provide the messaging and paging marketplace with a powerful and
flexible solution to carry communications design into the next millennium. The MMC2080 integrates two
of Motorola’s most successful product families, MCORE and the Roaming FLEX alphanumeric
decoders, a combination that will set a new standard in the communications industry. Except for the FLEX
decoder, the MMC2075 offers all features of the MMC2080.
Both the The MMC2080/2075 are members of the low-power, high-performance MCORE family of 32-bit
microcontroller units (MCUs). The MCORE is a streamlined execution engine that provides many of the
performance enhancements found in mainstream reduced instruction set computers (RISCs). Combining
performance, speed, and cost efficiency in a compact, low-power design, the MCORE microRISC
architecture is a natural solution for applications where battery life and systems cost are critical design goals.
Given that a total system’s components and processor core determine its power consumption, the instruction
set architecture (ISA) for the MCORE is designed to optimize the trade-off between performance and total
power consumption. The result is system-wide reduction of total energy consumption with maintenance of
acceptable performance levels. Memory power consumption (both on-chip and external) is a major factor in
system energy consumption. By adopting 16-bit instruction encoding, and thus significantly decreasing the
memory bandwidth needed for a high rate of instruction execution, the MMC2080/2075 minimizes the
overhead of memory system energy consumption.
The MMC2080/2075 also reduces power consumption by coupling a fully static design with dynamic power
management and low-voltage operation. Versatile power management is achieved through automatic power
downs of any internal functional blocks not needed on a clock-by-clock basis. Power conservation modes
are also provided for absolute power conservation.
A table of contents for this document appears on the following page. Figure 1 on page 3 and Figure 2 on
page 4 provide simplified block diagrams of the MMC2080/2075.
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