參數(shù)資料
型號(hào)： ML53612
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange
中文描述： 64通道全雙工H.100/H.110 CT總線系統(tǒng)接口和時(shí)隙交換
文件頁(yè)數(shù)： 9/68頁(yè)
文件大?。?/td> 696K
代理商： ML53612
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I
ML53612
I
5
Oki Semiconductor
3.0 SIGNAL DESCRIPTIONS
Signal Description
[1]
Name
Description
D_[7:0]
Microprocessor Data Bus. (I/O, TTL Schmitt, 8 mA, 5V tolerant)
A_ [7:0]
Microprocessor Address Bus. (Input, TTL Schmitt, 5V tolerant)
ALE (AS)
Intel Bus Mode - Address Latch Enable. Motorola Bus Mode - Address Strobe. The Microprocessor Address Bus A[9:0] is latched
internally on the falling edge of this signal. (Input, TTL Schmitt, 5V tolerant)
CS_N
Chip Select. This active low signal selects the ML53612 for a microprocessor read or write operation. (Input, TTL Schmitt, 5V
tolerant)
RD_N (STRB_N)
Intel Bus Mode - Microprocessor Bus Read. Motorola Bus Mode - Microprocessor Bus Strobe. (Input, TTL Schmitt, 5V tolerant)
WR_N (R/W_N)
Intel Bus Mode - Microprocessor Bus Write. Motorola Bus Mode - Microprocessor Bus Read/Write signal.
(Input, TTL Schmitt, 5V tolerant)
RESET
Reset. This active high input signal initializes the microprocessor interface, configuration, and routing registers. (Input, TTL
Schmitt, 5V tolerant)
I_N (M)
Microprocessor Bus Mode. When this input is low, Intel Bus Mode is selected. When this input is high, Motorola Bus Mode is
selected. (Input, TTL Schmitt, 5V tolerant)
CT_D_DISABLE
CT_D Global disable. (I/O, TTL Schmitt, 8 mA, 50 k Pull Up, 5V tolerant)
L_NETREF_[1:0]
Local Network Reference [1:0] Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
L_SI_[1:0]
Local bus Serial Input Data Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
MC_TXD
Message Channel Transmit Data Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
APLL_CLKREF
Analog PLL Clock Reference Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
APLL_VDDO
+3.3 Volt Analog PLL I/O Power Supply
APLL_VDDC
+3.3 Volt Analog PLL Core Power Supply
APLL_PC
Analog PLL Phase Comparator Analog Output
APLL_VCO
Analog PLL VCO Analog Input
APLL_VSSC
Analog PLL Core Ground
APLL_VSSO
Analog PLL I/O Ground
APLL_TEST
Analog PLL Test Enable Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
TEST
Test Select. This input enables the pin continuity test. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
TMS
Test Access Port Mode Select. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
TCK
Test Access Port Clock. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
TRST_N
Test Access Port Reset. (active low). (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
TDI
Test Access Port Data Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
INT
Interrupt Output. (I/O, TTL Schmitt, 50 k Pull Up, 8 mA, 5V tolerant)
CT_D_[31:0]
CT Bus Serial Data Streams. (I/O, PCI, 5V tolerant)
CT_FRAME_A_N
CT Bus "A" Frame Sync. (I/O, TTL Schmitt, 24 mA, 5V tolerant)
CT_C8_A
CT Bus "A" 8 MHz Clock. (I/O, TTL Schmitt, 24 mA, 5V tolerant)
CT_NETREF_1
CT Bus Network Reference 1. (I/O, PCI, 5V tolerant)
CT_NETREF_2
CT Bus Network Reference 2. (I/O, PCI, 5V tolerant)
CT_FRAME_B_N
CT Bus "B" Frame Sync. (I/O, TTL Schmitt, 24 mA, 5V tolerant)
CT_C8_B
CT Bus "B" 8 MHz Clock. (I/O, TTL Schmitt, 24 mA, 5V tolerant)
CT_MC
CT Bus Message Channel. (I/O, TTL Schmitt, 24 mA, 5V tolerant)
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