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參數(shù)資料
| 型號(hào)： | ML53612 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange |
| 中文描述： | 64通道全雙工H.100/H.110 CT總線系統(tǒng)接口和時(shí)隙交換 |
| 文件頁數(shù)： | 47/68頁 |
| 文件大?。?/td> | 696K |
| 代理商： | ML53612 |
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ML53612
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43
Oki Semiconductor
Note: Do not use Minimum delay mode on channels using parallel data source.
Note:
1. When CT Bus Connect is enabled, the L_SO to L_SI connection does not pass through the conversion
circuitry. See Figure 2.
2. The Receive Switch Output Enable register does not have to be set to make this connection.
Note: The Serial TDM data and the parallel access register share common registers within the transmit switch.
Therefore it is necessary to write to the parallel access register after the source is changed to parallel
microprocessor data.
DR_2
Definition
0
Delay
1
CT Bus Connect
2
Source
[7:3]
Reserved (write zero)
Delay (Read/Write)
Selects the switching delay mode. When set to Constant, data is switched on frame boundaries resulting in a constant 1 frame delay and allowing
"bundling". When set to Minimum, data is switched on 2 Mbps time-slot boundaries reducing the delay through the switch for certain combinations of
input to output time-slots.
0
→
Constant (Default)
1
→
Minimum
CT Bus Connect Enable (Read/Write)
Enables the switch to be used for CT Bus to CT Bus connection without externally connecting L_SO to L_SI. When enabled, the L_SI input is replaced
by the corresponding L_SO output. CT Bus connect allows inter-operability switching to be provided by any unused transmit and receive switch pair.
0
→
CT Bus Connect Disabled (Default)
1
→
CT Bus Connect Enabled
Source (Read/Write)
Selects the transmit channel data source. When set to 0, Serial TDM data from L_SI or L_SO (see CT Bus Connect Enable) is selected. When set to 1,
the corresponding parallel access register is selected as the source of the transmit channel data.
0
→
Serial TDM data (Default)
1
→
Parallel microprocessor data
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