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參數(shù)資料
| 型號(hào)： | ML53612 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange |
| 中文描述： | 64通道全雙工H.100/H.110 CT總線系統(tǒng)接口和時(shí)隙交換 |
| 文件頁(yè)數(shù)： | 54/68頁(yè) |
| 文件大?。?/td> | 696K |
| 代理商： | ML53612 |
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ML53612
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50
Oki Semiconductor
6.4 AC Electrical Characteristics
Note: Signals ending in “_N” are active low.
Microprocessor Interface Timing - Intel Bus Mode, Non-multiplexed Address
[1]
[2]
[3]
1.
2.
3.
Timing measured with 100 pF load on D_[7:0].
Write cycle may be controlled by CS_N or WR_N.
ALE=1.
Parameter
Symbol
Min
Typ
Max
Unit
CS_N setup to WR_N
↑
t1
40
ns
WR_N pulse width
t2
40
ns
A_[9:0] setup to WR_N
↓
(C_96=1)
t3
5
ns
A_[2:0] setup to WR_N
↑
(C_96=0)
t4
40
ns
A_[9:0] hold from WR_N
↑
t5
5
ns
D_[7:0] setup to WR_N
↑
t6
40
ns
D_[7:0] hold from WR_N
↑
t7
5
ns
D_[7:0] float to valid delay from CS_N RD_N, and A_[9:0]
t8
0
50
ns
D_[7:0] valid to float delay from CS_N or RD_N
t9
0
10
ns
Figure 7. Microprocessor Interface Timing - Intel Bus Mode, Non-multiplexed Address
CS_N
RD_N
WR_N
A_[9:0]
D_[7:0]
t1
t2
t4
t3
t5
t7
t6
t8
t9
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