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參數(shù)資料
| 型號： | ML53612 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange |
| 中文描述： | 64通道全雙工H.100/H.110 CT總線系統(tǒng)接口和時隙交換 |
| 文件頁數(shù)： | 63/68頁 |
| 文件大小： | 696K |
| 代理商： | ML53612 |
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ML53612
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59
Oki Semiconductor
6.6 Clock Skew Requirements
(Extract from H.100/H.110 Specifications, Rev. 1.0)
Parameter
Symbol
Min
Typ
Max
Unit
Notes
(H.100) Max Skew between CT_C8 "A" and "B"
Tskc8
±10 ±
Φ
ns
[1] [2] [3] [4]
1.
2.
3.
Test Load – 200 pF.
Assumes "A" and "B" masters in adjacent slots.
When static skew is 10nS and, in the same clock cycle, each clock performs a 10nS phase correction in opposite directions, a maximum skew of
30nS will occur during that clock cycle.
Meeting the skew requirements in Table 2 and the requirements of Section 2.3 (in the H.100/H.110 Specifications, Rev. 1.0) could require the
PLL’s generating CT_C8 to have different time constants when acting as primary and secondary clock masters.
Test Load - "A" load = "B" load.
4.
(H.110) Max Skew between CT_C8 "A" and "B"
Tskc8
±10 ±
Φ
ns
[2] [3] [4] [5]
5.
(H.100) Max Skew between CT_C8_A and any
compatibility clock
Tskcomp
±5
ns
[1]
(H.110) Max Skew between CT_C8_A and any
compatibility clock
Tskcomp
±5
ns
[5]
Figure 15. Clock Skew Requirements
CT_C8_A
CT_C8_B
Vt+
Vt+
Tskc8
CT_C8_A
Inter-operability Clocks
Vt+
Vt+
Vt-
Tskcomp
Tskcomp
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