參數(shù)資料
型號： ML53612
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange
中文描述： 64通道全雙工H.100/H.110 CT總線系統(tǒng)接口和時隙交換
文件頁數(shù)： 61/68頁
文件大小： 696K
代理商： ML53612
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
I
ML53612
I
57
Oki Semiconductor
6.5 H.100/H.110 Bus Timing Specification
(Extract from H.100/H.110 Specifications, Rev. 1.0)
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Clock edge rate (All Clocks)
H.100
0.25
2
V/ns
[1]
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Test Load - 12 pF
11. Measured at the receiver.
12. Reference only: Tdv = Max. clock cable delay + Max. data cable delay + Max. data HiZ to output time = 12nS + 35nS + 22 nS = 69nS. Max. clock
cable delay and max. data cable delay are worst case numbers based on electrical simulation.
13. Reference only: Tdv = Max. clock backplane delay + Max. data backplane delay + Max. data HiZ to output time = 26nS + 46nS + 11nS = 83nS. Max.
clock delay and max. data delay are worst case numbers based on electrical simulation.
14. Based on worst case electrical simulation.
15. This range accounts for
Φ
(Phase Correction).
16. Tcell = Max. clock backplane delay + Max. data backplane delay + Max. Tzdo + (Min. Tdiv - Max. Tdv) + Max Tdoz + F = 26nS + 46nS + 11nS +
(102nS - 83nS) + 10nS + 10nS = 122nS. Max. clock delay and max. data delay are worst case numbers based on electrical simulation.
The rise and fall times are determined by the edge rate in V/nS. A maximum edge rate is the fastest rate at which a clock transitions.
10% - 90%. Test Load = 150 pF.
Tc8p Min and Max are under free-run conditions assuming ±32 ppm clock accuracy.
Non-cumulative, Tc8p requirements still need to be met.
Duty Cycle measured at transmitter under no load conditions.
For reference only
Test Load - 200 pF
Measured at the transmitter.
Tdoz and Tzdo apply at every time-slot boundary.
CT_C8_(A/B) and CT_FRAME_(A/B)_N
edge rate
H.110
0.25
2
V/ns
[1]
CT_NETREF edge rate
H.110
0.3
V/ns
[2]
Clock CT_C8_(A/B) Period
Tc8p
122.066-
Φ
122.074+
Φ
ns
[3]
Clock CT_C8_(A/B) High Time
H.100
Tc8h
49-
Φ
73+
Φ
ns
[4]
H.110
63-
Φ
69+
Φ
ns
[4]
[5]
Clock CT_C8_(A/B) Low Time
H.100
Tc8l
49-
Φ
73+
Φ
ns
[4]
H.110
63-
Φ
69+
Φ
ns
[4]
[5]
Data Sample Point
Tsamp
90
ns
[6]
Data Output to HiZ Time
H.100
Tdoz
-20
0
ns
[7] [8]
[9]
H.110
-10
0
ns
[8]
[9]
[10]
Data HiZ to Output Time
H.100
Tzdo
0
22
ns
[7]
[8] [9]
H.110
0
11
ns
[8] [9]
[10]
Data Output Delay Time
H.100
Tdod
0
22
ns
[7]
[8]
H.110
0
11
ns
[8]
[10]
Data Valid Time
H.100
Tdv
0
69
ns
[7]
[11]
[12]
H.110
0
83
ns
[11] [13]
[14]
Data Invalid Time
H.100
Tdiv
102
112
ns
H.110
102
112
ns
[15]
[16]
CT_FRAME_(A/B)_N Width
Tfp
90
122
180
ns
CT_FRAME_(A/B)_N Setup Time
Tfs
45
90
ns
CT_FRAME_(A/B)_N Hold Time
Tfh
45
90
ns
Phase Correction
Φ
0
10
ns
[17]
相關(guān)PDF資料
PDF描述
ML60851D USB Device Controller
ML60852 USB Device Controller
ML6190A Longwave Time Code RF Receiver LSI
ML63187 4-Bit Microcontroller with Built-in 1024-Dot Matrix LCD Drivers and Melody Circuit, Operating at 0.9 V (Min).
ML63189B 4-Bit Microcontroller with Built-in 1024-Dot Matrix LCD Drivers and Melody Circuit, Operating at 0.9 V (Min).
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ML536RATR42_LZ 制造商:COILCRAFT 制造商全稱:Coilcraft lnc. 功能描述:High-Reliability Air Core Inductors
ML53812-2 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:H.100/H.110 CT Bus System Interface and Time-Slot Interchange
ML53812-2TC 制造商:ROHM Semiconductor 功能描述:
ML53FAD 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:Micropower CMOS Oscillators
ML53FAG 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:Micropower CMOS Oscillators
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*