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參數(shù)資料
| 型號： | ML53612 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange |
| 中文描述： | 64通道全雙工H.100/H.110 CT總線系統(tǒng)接口和時隙交換 |
| 文件頁數(shù)： | 25/68頁 |
| 文件大?。?/td> | 696K |
| 代理商： | ML53612 |
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–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
I
ML53612
I
21
Oki Semiconductor
Configuration Register Byte 4, AR = 0004h
DR_0
C
Definition
[2:0]
[34:32]
Master PLL Mode [2:0]
3
35
Reserved
[5:4]
[37:36]
Master PLL Mode Read-back [1:0]
6
38
Condition Master PLL Reference
7
39
Reserved
Master PLL Mode [2:0] (C_ [34:32]) (Read/Write)
[1]
1.
Master PLL error occurs when the Master PLL is out of lock with its reference signal. It is necessary to manually select "Normal" to go back to
normal operation after an auto switch has occurred.
000
001
010
011
100
101
110
111
→
→
→
→
→
→
→
→
Normal (Default)
Reserved
Holdover
Free Run
Reserved
Reserved
Auto Normal to Holdover switch on Master PLL error
Auto Normal to Free Run switch on Master PLL error
Master PLL Mode Read-back [1:0] (C_ [37:36]) (Read Only)
00
01
10
11
→
→
→
→
Normal
Reserved
Holdover
Free Run
Condition Master PLL Reference (C_ [38]) (Read/Write)
When enabled, conditions a change in references for MTIE compatibility.
0
→
Condition Master PLL Reference Disabled (Default)
1
→
Condition Master PLL Reference Enabled
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