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參數(shù)資料
| 型號： | ML53612 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange |
| 中文描述： | 64通道全雙工H.100/H.110 CT總線系統(tǒng)接口和時隙交換 |
| 文件頁數(shù)： | 16/68頁 |
| 文件大?。?/td> | 696K |
| 代理商： | ML53612 |
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ML53612
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Oki Semiconductor
4.17 GPIO Ports
Four general purpose input/output ports are provided. The ports may be individually configured to a
variety of modes and can also be used as interrupt sources. Possible uses of the GPIO ports would be con-
trolling H.100/H.110 termination switches or implementing the SCbus CLKFAIL signal.
4.18 Message Channel
The ML53612 provides a complete interface between the CT_MC CT Bus signal and a local HDLC con-
troller. This includes generation of MC_CLK as well as buffering of MC_TXD and MC_RXD.
4.19 Law/Linear Conversion & Gain
Law/Linear conversion and/or gain are selected independently per time-slot.
The following conversions are supported:
A to μ
μ to A
A to Linear
μ to Linear
Linear to μ
Linear to A
A to μ and μ to A conversions are G.711 compliant (when "No gain" is selected).
Gain may be selected over a range of ± 31 dB in 1dB steps.
When conversion or gain is selected there will be an additional 1 frame (125 ms) delay through the
device. To minimize delay, channels that do not require conversion or gain may by-pass the conversion
and gain circuitry.
Figure 4. CT_C8_A and CT_C8_B Error Detection
CT_C8_(A/B)
Expected Delay (Approx. 125 ns)
Late Allowance (35 ns)
Rising edge of CT_C8 occurring
after this limit will trigger an
interrupt (if enabled).
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