參數(shù)資料
型號: MC705JP7CPE
廠商: Freescale Semiconductor
文件頁數(shù): 42/164頁
文件大小: 0K
描述: IC MCU 8BIT 224 BYTES RAM 28PDIP
標(biāo)準(zhǔn)包裝: 13
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設(shè)備: POR,溫度傳感器,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 6KB(6K x 8)
程序存儲器類型: OTP
RAM 容量: 224 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.600",15.24mm)
包裝: 管件
Instruction Set
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
136
Freescale Semiconductor
14.5 Opcode Map
TAX
Transfer
Accumulator to Index
Register
X
← (A)
— ————
INH
97
2
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte for
Negative or Zero
(M) – $00
— ————
DIR
INH
IX1
IX
3D
4D
5D
6D
7D
dd
ff
4
3
5
4
TXA
Transfer Index
Register to
Accumulator
A
← (X)
— ————
INH
9F
2
WAIT
Stop CPU Clock and
Enable
Interrupts
———
INH
8F
2
A
Accumulator
opr
Operand (one or two bytes)
C
Carry/borrow flag
PC
Program counter
CCR Condition code register
PCH Program counter high byte
dd
Direct address of operand
PCL
Program counter low byte
dd rr
Direct address of operand and relative offset of branch instruction
REL
Relative addressing mode
DIR
Direct addressing mode
rel
Relative program counter offset byte
ee ff
High and low bytes of offset in indexed, 16-bit offset addressing
rr
Relative program counter offset byte
EXT
Extended addressing mode
SP
Stack pointer
ff
Offset byte in indexed, 8-bit offset addressing
X
Index register
H
Half-carry flag
Z
Zero flag
hh ll
High and low bytes of operand address in extended addressing
#
Immediate value
I
Interrupt mask
Logical AND
ii
Immediate operand byte
Logical OR
IMM
Immediate addressing mode
Logical EXCLUSIVE OR
INH
Inherent addressing mode
( )
Contents of
IX
Indexed, no offset addressing mode
–( )
Negation (two’s complement)
IX1
Indexed, 8-bit offset addressing mode
Loaded with
IX2
Indexed, 16-bit offset addressing mode
?
If
M
Memory location
:
Concatenated with
N
Negative flag
Set or cleared
n
Any bit
Not affected
Table 14-6. Instruction Set Summary (Sheet 6 of 6)
Source
Form
Operation
Description
Effect
on CCR
Addres
s
Mo
de
Op
co
de
Op
erand
Cycles
HIN Z C
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