參數(shù)資料
型號： MC705JP7CPE
廠商： Freescale Semiconductor
文件頁數(shù)： 117/164頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 224 BYTES RAM 28PDIP
標準包裝： 13
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-DIP（0.600"，15.24mm）
包裝： 管件
Parallel Input/Output
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
56
Freescale Semiconductor
7.2.2 Data Direction Register A
The contents of the port A data direction register (DDRA) determine whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the associated port A pin. A
DDRA bit set to a logic 1 also disables the pulldown device for that pin. Writing a logic 0 to a DDRA bit
disables the output buffer for the associated port A pin. The upper two bits always read as logic 0s. A reset
initializes all DDRA bits to logic 0s, configuring all port A pins as inputs and disabling the voltage
comparators from driving PA4 or PA5.
DDRA5–DDRA0 — Port A Data Direction Bits
These read/write bits control port A data direction. Reset clears the DDRA5–DDRA0 bits.
1 = Corresponding port A pin configured as output and pulldown device disabled
0 = Corresponding port A pin configured as input
7.2.3 Pulldown Register A
All port A pins can have software programmable pulldown devices enabled or disabled globally by SWPDI
bit in the MOR. These pulldown devices are controlled by the write-only pulldown register A (PDRA)
shown in Figure 7-3. Clearing the PDIA5–PDIA0 bits in the PDRA turns on the pulldown devices if the port
A pin is an input. Reading the PDRA returns undefined results since it is a write-only register; therefore,
do not change the value in PDRA with read/modify/write instructions. On the MC68HC705JP7 the PDRA
contains two pulldown control bits (PDICH and PDICL) for port C. Reset clears the PDIA5–PDIA0, PDICH,
and PDICL bits, which turns on all the port A and port C pulldown devices.
PDICH — Upper Port C Pulldown Inhibit Bits (MC68HC705JP7)
Writing to this write-only bit controls the port C pulldown devices on the upper four bits (PC4–PC7).
Reading these pulldown register A bits returns undefined data. Reset clears bit PDICH.
1 = Upper four port C pins pulldown devices turned off
0 = Upper four port C pins pulldown devices turned on if pin has been programmed by the DDRC
to be an input
Address:
$0004
Bit 7
654321
Bit 0
Read:
0
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Write:
Reset:
00000000
= Unimplemented
Figure 7-2. Data Direction Register A (DDRA)
Address:
$0010
Bit 7
654321
Bit 0
Read:
Write:
PDICH
PDICL
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
Reset:
00000000
= Unimplemented
Figure 7-3. Pulldown Register A (PDRA)
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參數(shù)描述
MC705JP7CPE 制造商:Freescale Semiconductor 功能描述:IC 8BIT MCU 68HC05 2.1MHZ DIP-28
MC705K1CP 制造商:Motorola Inc 功能描述:16 PIN DIP INTEGRATED CIRCUIT
MC705L16CFUE 功能描述:8位微控制器 -MCU 8B MCU W/ EPROM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MC705P6ACDWE 功能描述:8位微控制器 -MCU MCU 176 BYTES RAM A/D RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MC705P6ACDWE 制造商:Freescale Semiconductor 功能描述:8-Bit Microcontroller IC
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