參數(shù)資料
型號： MC705JP7CPE
廠商： Freescale Semiconductor
文件頁數(shù)： 162/164頁
文件大小： 0K
描述： IC MCU 8BIT 224 BYTES RAM 28PDIP
標(biāo)準(zhǔn)包裝： 13
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-DIP（0.600"，15.24mm）
包裝： 管件
SIOP Registers
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
97
9.2.2 Serial Data Input (SDI)
The SDI pin becomes an input as soon as the SIOP subsystem is enabled. New data is presented to the
SDI pin on the falling edge of SCK. Valid data must be present at least 100 nanoseconds before the rising
edge of SCK and remain valid for 100 nanoseconds after the rising edge of SCK. See Figure 9-3.
9.2.3 Serial Data Output (SDO)
The SDO pin becomes an output as soon as the SIOP subsystem is enabled. The state of the PB5/SDO
pin reflects the value of the first bit received on the previous transmission. Prior to enabling the SIOP, the
PB5/SDO can be initialized to determine the beginning state. While SIOP is enabled, the port B logic
cannot be used as a standard output since that pin is connected to the last stage of the SIOP serial shift
register. A control bit (LSBF) is included in the SCR to allow the data to be transmitted in either the MSB
first format or the LSB first format.
The first data bit will be shifted out to the SDO pin on the first falling edge of the SCK. The remaining data
bits will be shifted out to the SDI pin on subsequent falling edges of SCK. The SDO pin will present valid
data at least 100 nanoseconds before the rising edge of the SCK and remain valid for 100 nanoseconds
after the rising edge of SCK. See Figure 9-3.
9.3 SIOP Registers
The SIOP is programmed and controlled by the SIOP control register (SCR) located at address $000A,
the SIOP status register (SSR) located at address $000B, and the SIOP data register (SDR) located at
address $000C.
9.3.1 SIOP Control Register (SCR)
The SIOP control register (SCR) is located at address $000A and contains seven control bits and a
write-only reset of the interrupt flag. Figure 9-4 shows the position of each bit in the register and indicates
the value of each bit after reset.
SPIE — Serial Peripheral Interrupt Enable Bit
The SPIE bit enables the SIOP to generate an interrupt whenever the SPIF flag bit in the SSR is set.
Clearing the SPIE bit will not affect the state of the SPIF flag bit and will not terminate a serial interrupt
once the interrupt sequence has started. Reset clears the SPIE bit.
1 = Serial interrupt enabled
0 = Serial interrupt disabled
NOTE
If the SPIE bit is cleared just after the serial interrupt sequence has started
(for instance, the CPU status is being stacked), then the CPU will be unable
Address:
$000A
Bit 7
654321
Bit 0
Read:
SPIE
SPE
LSBF
MSTR
0
CPHA
SPR1
SPR0
Write:
SPIR
Reset:
00000000
Figure 9-4. SIOP Control Register (SCR)
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參數(shù)描述
MC705JP7CPE 制造商:Freescale Semiconductor 功能描述:IC 8BIT MCU 68HC05 2.1MHZ DIP-28
MC705K1CP 制造商:Motorola Inc 功能描述:16 PIN DIP INTEGRATED CIRCUIT
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MC705P6ACDWE 制造商:Freescale Semiconductor 功能描述:8-Bit Microcontroller IC
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