參數資料
型號: MC705JP7CPE
廠商: Freescale Semiconductor
文件頁數: 152/164頁
文件大小: 0K
描述: IC MCU 8BIT 224 BYTES RAM 28PDIP
標準包裝: 13
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設備: POR,溫度傳感器,WDT
輸入/輸出數: 22
程序存儲器容量: 6KB(6K x 8)
程序存儲器類型: OTP
RAM 容量: 224 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數據轉換器: A/D 4x12b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.600",15.24mm)
包裝: 管件
Analog Subsystem
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
88
Freescale Semiconductor
Figure 8-11. A/D Conversion — OCF/ICF Control (Mode 3)
Point
Action
Software/Hardware Action
Dependent Variable(s)
0
Begin initial discharge and select mode 3 by
clearing CHG and setting ATD2 and ATD1 in
the ACR. Also set ICEN bit in ACR and IEDG
bit in TCR.
Software write
Software
1
VCAP falls to VSS. Set timer output compare
registers (OCRH and OCRL) to desired
charge start time.
Wait out minimum tDIS time.
Software write to OCRH, OCRL
VMAX, IDIS, CEXT, software
2
Stop discharge and begin charge when the
next OCF sets the CHG control bit in ACR.
Timer OCF sets the CHG control bit
in the ACR.
Free-running timer
output compare, fOSC
3
VCAP rises to VX and comparator 2 output
trips, setting CPF2 and CMP2, which causes
an ICF from the timer and clears the CHG
control bit in ACR. Must clear CPF2 to trap
next CPF2 flag. Load next OCF.
Wait out tCHG time.
Timer ICF clears the CHG control bit
in the ACR.
VX, ICHG, CEXT
tDIS
(MIN)
tCHG x ICHG
CEXT
tCHG
tDIS
VX =
VMAX
CHG
COMP2
0
TOF
OCF
ICF
(MIN)
VCAP
tDIS
VX
1
2
3
1
2
(TCAP)
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