參數(shù)資料
型號: MC705JP7CPE
廠商: Freescale Semiconductor
文件頁數(shù): 134/164頁
文件大小: 0K
描述: IC MCU 8BIT 224 BYTES RAM 28PDIP
標準包裝: 13
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設備: POR,溫度傳感器,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 6KB(6K x 8)
程序存儲器類型: OTP
RAM 容量: 224 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.600",15.24mm)
包裝: 管件
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
71
Chapter 8
Analog Subsystem
8.1 Introduction
The analog subsystem of the MC68HC705JJ7/MC68HC705P7 is based on two on-chip voltage
comparators and a selectable current charge/discharge function as shown in Figure 8-1.
This configuration provides several features:
Two independent voltage comparators with external access to both inverting and non-inverting
inputs
One voltage comparator can be connected as a single-slope analog-to-digital (A/D) and the other
connected as a single-voltage comparator. The possible single-slope A/D connection provides
these features:
A/D conversions can use VDD or an external voltage as a reference with software used to
calculate ratiometric or absolute results
Channel access of up to four inputs via multiplexer control with independent multiplexer control
allowing mixed input connections
Access to VDD and VSS for calibration
Divide by 2 to extend input voltage range
Each comparator can be inverted to calculate input offsets.
Internal sample and hold capacitor
Direct digital output of comparator 1 to the PB4 pin
Voltages are resolved by measuring the time it takes an external capacitor to charge up to the level of the
unknown input voltage being measured. The beginning of the A/D conversion time can be started by
several means:
Output compare from the 16-bit programmable timer
Timer overflow from the 16-bit programmable timer
Direct software control via a register bit
The end of the A/D conversion time can be captured by these means:
Input capture in the 16-bit programmable timer
Interrupt generated by the comparator output
Software polling of the comparator output using software loop time
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