參數(shù)資料
型號: MC68LNC705C9ACFN
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 36/177頁
文件大小: 1941K
代理商: MC68LNC705C9ACFN
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M
C68
HC705C9A
Rev.
4.0
130
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Table 11-7. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
REL
DIR
INH
IX1
IX
INH
IMM
DIR
EXT
IX2
IX1
IX
0
1
23
45
6
7
8
9
A
B
C
D
E
F
0
5
BRSET0
3DIR
5
BSET0
2DIR
3
BRA
2REL
5
NEG
2DIR
3
NEGA
1INH
3
NEGX
1INH
6
NEG
2IX1
5
NEG
1IX
9
RTI
1INH
2
SUB
2IMM
3
SUB
2DIR
4
SUB
3EXT
5
SUB
3IX2
4
SUB
2IX1
3
SUB
1IX
0
1
5
BRCLR0
3DIR
5
BCLR0
2DIR
3
BRN
2REL
6
RTS
1INH
2
CMP
2IMM
3
CMP
2DIR
4
CMP
3EXT
5
CMP
3IX2
4
CMP
2IX1
3
CMP
1IX
1
2
5
BRSET1
3DIR
5
BSET1
2DIR
3
BHI
2REL
11
MUL
1INH
2
SBC
2IMM
3
SBC
2DIR
4
SBC
3EXT
5
SBC
3IX2
4
SBC
2IX1
3
SBC
1IX
2
3
5
BRCLR1
3DIR
5
BCLR1
2DIR
3
BLS
2REL
5
COM
2DIR
3
COMA
1INH
3
COMX
1INH
6
COM
2IX1
5
COM
1IX
10
SWI
1INH
2
CPX
2IMM
3
CPX
2DIR
4
CPX
3EXT
5
CPX
3IX2
4
CPX
2IX1
3
CPX
1IX
3
4
5
BRSET2
3DIR
5
BSET2
2DIR
3
BCC
2REL
5
LSR
2DIR
3
LSRA
1INH
3
LSRX
1INH
6
LSR
2IX1
5
LSR
1IX
2
AND
2IMM
3
AND
2DIR
4
AND
3EXT
5
AND
3IX2
4
AND
2IX1
3
AND
1IX
4
5
5
BRCLR2
3DIR
5
BCLR2
2DIR
3
BCS/BLO
2REL
2
BIT
2IMM
3
BIT
2DIR
4
BIT
3EXT
5
BIT
3IX2
4
BIT
2IX1
3
BIT
1IX
5
6
5
BRSET3
3DIR
5
BSET3
2DIR
3
BNE
2REL
5
ROR
2DIR
3
RORA
1INH
3
RORX
1INH
6
ROR
2IX1
5
ROR
1IX
2
LDA
2IMM
3
LDA
2DIR
4
LDA
3EXT
5
LDA
3IX2
4
LDA
2IX1
3
LDA
1IX
6
7
5
BRCLR3
3DIR
5
BCLR3
2DIR
3
BEQ
2REL
5
ASR
2DIR
3
ASRA
1INH
3
ASRX
1INH
6
ASR
2IX1
5
ASR
1IX
2
TAX
1INH
4
STA
2DIR
5
STA
3EXT
6
STA
3IX2
5
STA
2IX1
4
STA
1IX
7
8
5
BRSET4
3DIR
5
BSET4
2DIR
3
BHCC
2REL
5
ASL/LSL
2DIR
3
ASLA/LSLA
1INH
3
ASLX/LSLX
1INH
6
ASL/LSL
2IX1
5
ASL/LSL
1IX
2
CLC
1INH
2
EOR
2IMM
3
EOR
2DIR
4
EOR
3EXT
5
EOR
3IX2
4
EOR
2IX1
3
EOR
1IX
8
9
5
BRCLR4
3DIR
5
BCLR4
2DIR
3
BHCS
2REL
5
ROL
2DIR
3
ROLA
1INH
3
ROLX
1INH
6
ROL
2IX1
5
ROL
1IX
2
SEC
1INH
2
ADC
2IMM
3
ADC
2DIR
4
ADC
3EXT
5
ADC
3IX2
4
ADC
2IX1
3
ADC
1IX
9
A
5
BRSET5
3DIR
5
BSET5
2DIR
3
BPL
2REL
5
DEC
2DIR
3
DECA
1INH
3
DECX
1INH
6
DEC
2IX1
5
DEC
1IX
2
CLI
1INH
2
ORA
2IMM
3
ORA
2DIR
4
ORA
3EXT
5
ORA
3IX2
4
ORA
2IX1
3
ORA
1IX
A
B
5
BRCLR5
3DIR
5
BCLR5
2DIR
3
BMI
2REL
2
SEI
1INH
2
ADD
2IMM
3
ADD
2DIR
4
ADD
3EXT
5
ADD
3IX2
4
ADD
2IX1
3
ADD
1IX
B
C
5
BRSET6
3DIR
5
BSET6
2DIR
3
BMC
2REL
5
INC
2DIR
3
INCA
1INH
3
INCX
1INH
6
INC
2IX1
5
INC
1IX
2
RSP
1INH
2
JMP
2DIR
3
JMP
3EXT
4
JMP
3IX2
3
JMP
2IX1
2
JMP
1IX
C
D
5
BRCLR6
3DIR
5
BCLR6
2DIR
3
BMS
2REL
4
TST
2DIR
3
TSTA
1INH
3
TSTX
1INH
5
TST
2IX1
4
TST
1IX
2
NOP
1INH
6
BSR
2REL
5
JSR
2DIR
6
JSR
3EXT
7
JSR
3IX2
6
JSR
2IX1
5
JSR
1IX
D
E
5
BRSET7
3DIR
5
BSET7
2DIR
3
BIL
2REL
2
STOP
1INH
2
LDX
2IMM
3
LDX
2DIR
4
LDX
3EXT
5
LDX
3IX2
4
LDX
2IX1
3
LDX
1IX
E
F
5
BRCLR7
3DIR
5
BCLR7
2DIR
3
BIH
2REL
5
CLR
2DIR
3
CLRA
1INH
3
CLRX
1INH
6
CLR
2IX1
5
CLR
1IX
2
WAIT
1INH
2
TXA
1INH
4
STX
2DIR
5
STX
3EXT
6
STX
3IX2
5
STX
2IX1
4
STX
1IX
F
INH = Inherent
REL = Relative
IMM = Immediate
IX = Indexed, No Offset
DIR = Direct
IX1 = Indexed, 8-Bit Offset
EXT = Extended
IX2 = Indexed, 16-Bit Offset
0
MSB of Opcode in Hexadecimal
LSB of Opcode in Hexadecimal
0
5
BRSET0
3DIR
Number of Cycles
Opcode Mnemonic
Number of Bytes/Addressing Mode
LSB
MSB
LSB
MSB
LSB
MSB
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