參數(shù)資料
型號: MC68LNC705C9ACFN
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 133/177頁
文件大?。?/td> 1941K
代理商: MC68LNC705C9ACFN
Resets
RESET Pin
MC68HC705C9A — Rev. 4.0
Advance Information
MOTOROLA
Resets
59
5.4 RESET Pin
The function of the RESET pin is dependent on whether the device is
configured as an MC68HC05C9A or an MC68HC05C12A. When it is in
the MC68HC05C12A configuration, the pin is input only. When in
MC68HC05C9A configuration the pin is bidirectional. In both cases the
MCU is reset when a logic 0 is applied to the RESET pin for a period of
one and one-half machine cycles (t
RL
). For the MC68HC05C9A
configuration, the RESET pin will be driven low by a COP, clock monitor,
or power-on reset.
Figure 5-2. Power-On Reset and RESET
RESET
OSC1
2
INTERNAL
CLOCK
1
INTERNAL
ADDRESS
BUS
1
V
DD
INTERNAL
DATA
BUS
1
t
RL
NEW
PCH
NEW
PCL
OP
CODe
OP
CODE
PCH
PCL
3
t
CYC
4064t
CYC
t
VDDR
DUMMY
3FFF
NEW
PC
NEW
PC
3FFE
NEW
PC
NEW
PC
3FFE
3FFF
3FFE
DUMMY
Notes:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is only meant to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
t
RL
3
RESET
(C9A)
(C12A)
4
4. RESET outputs VOL during 4064 power-on reset cycles when in C9A mode only.
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