參數(shù)資料
型號: MC68LNC705C9ACFN
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 159/177頁
文件大?。?/td> 1941K
代理商: MC68LNC705C9ACFN
Capture/Compare Timer
Advance Information
MC68HC705C9A — Rev. 4.0
82
Capture/Compare Timer
MOTOROLA
8.4.6 Output Compare Registers
When the value of the 16-bit counter matches the value in the output
compare registers (OCRH and OCRL), the planned TCMP pin action
takes place. Writing to OCRH before writing to OCRL inhibits timer
compares until OCRL is written. Reading or writing to OCRL after the
timer status register clears the output compare flag (OCF).
Figure 8-7. Output Compare Registers (OCRH and OCRL)
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use this procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code register.
OCRH
$0016
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read:
Reset:
Unaffected by reset
OCRL
$0017
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Unaffected by reset
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