viii
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
11.5
Mode 3: 8-bit PWM with 256 Clock Prescaler ..............................................
11-12
11.5.1
Operation of Pulse Width Modulation Unit in Mode 3 .............................
11-12
11.5.2
Operation of Pulse Accumulator Unit in Mode 3 ....................................
11-13
11.5.3
Register Functions in Mode 3 .................................................................
11-14
11.5.3.1
Counter 1 (EVCNT1) ........................................................................
11-14
11.5.3.2
Compare Register 1A (ECMP1A) .....................................................
11-14
11.5.3.3
Compare Register 1B (ECMP1B) .....................................................
11-14
11.5.3.4
Counter 2 (EVCNT2) ........................................................................
11-14
11.5.3.5
Compare Register 2A (ECMP2A) .....................................................
11-14
11.5.3.6
Compare Register 2B (ECMP2B) .....................................................
11-14
11.5.3.7
Input Unit 1 (EVI1) ............................................................................
11-14
11.5.3.8
Input Unit 2 (EVI2) ............................................................................
11-15
11.5.3.9
Output Unit (EVO) .............................................................................
11-15
11.6
Event Counter Registers ..............................................................................
11-15
11.6.1
Counter Clock Register (EVCLK) ...........................................................
11-15
11.6.2
Counter Control Register (EVCTL) .........................................................
11-16
11.6.3
Counters Enable/Interrupt Mask Register (EVMSK) ..............................
11-17
11.6.4
Interrupt Flag Register (EVFLG) ............................................................
11-18
11.6.5
Counter Registers (EVCNTx) .................................................................
11-18
11.6.6
Counter Compare Registers (ECMPx) ...................................................
11-19
11.7
PWM using the Event Counter .....................................................................
11-19
11.8
Effective Range of the Set Up Values ..........................................................
11-19
11.9
Boundary Conditions of the PWM Function .................................................
11-20
Section 12
CPU, Addressing Modes and Instruction Set
12.1
Programming Model and CPU Registers .....................................................
12-1
12.1.1
Accumulators A and B ............................................................................
12-2
12.1.2
Index Register X (IX) ..............................................................................
12-2
12.1.3
Index Register Y (IY) ..............................................................................
12-2
12.1.4
Stack Pointer (SP) ..................................................................................
12-2
12.1.5
Program Counter (PC) ...........................................................................
12-2
12.1.6
Condition Code Register (CCR) .............................................................
12-2
12.2
Addressing Modes .......................................................................................
12-3
12.2.1
Immediate Addressing (IMM) .................................................................
12-3
12.2.2
Direct Addressing (DIR) .........................................................................
12-3
12.2.3
Extended Addressing (EXT) ...................................................................
12-4
12.2.4
Indexed Addressing (IND, X; IND, Y) .....................................................
12-4
12.2.5
Inherent Addressing (INH) ......................................................................
12-4
12.2.6
Relative Addressing (REL) .....................................................................
12-4
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Freescale Semiconductor, Inc.
For More Information On This Product,
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