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參數(shù)資料
| 型號： | MC68HC11G7CFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 114/195頁 |
| 文件大小： | 1940K |
| 代理商： | MC68HC11G7CFN |
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OPERATING MODES AND SIGNAL DESCRIPTION
2-7
2.2.3
Crystal Driver (XTAL) and External Clock Input (EXTAL)
These two pins provide the interface for either a crystal or a CMOS compatible clock to control the
internal clock generator circuitry. The frequency applied to these pins must be four times higher than
the desired E-clock rate. When a crystal is used, a 25 pF capacitor should be connected from each
of the XTAL and EXTAL pins to ground to ensure reliable start-up operation. When an external
CMOS compatible clock is used as an input to the EXTAL pin, the XTAL pin should be left
disconnected. However, a 10 k
to 100 k load resistor to ground may be used to reduce RFI noise
emission. (See Figure 2-1.)
2.2.4
E-clock Output (E)
The E-clock pin provides an output for the internally generated E-clock, which can be used as a
timing reference. The frequency of the E-clock output is one quarter of the input frequency at the
XTAL and EXTAL pins. When the E-clock output is low, an internal process is taking place; when
high, data is being accessed. The signal is halted when the MCU is in STOP mode.
2.2.5
Read/Write (R/W)
This pin is used to control the direction of transfers on the external data bus in expanded non-
multiplexed mode. A logic zero level indicates that data is being written to the external data bus; a
logic one level indicates that a read cycle is in progress. R/W stays high during single-chip
and bootstrap modes to maintain the ‘read’ state for systems which switch modes.
2.2.6
Interrupt Request (IRQ)
The IRQ pin provides the capability to apply asynchronous interrupts to the MC68HC11G5. It is
software selectable, (using the IRQE bit in the OPTION register) with a choice of either negative
edge sensitive or level sensitive triggering, and is always configured to level sensitive by reset. This
pin requires an external pull-up resistor connected to VDD.
2.2.7
Non-Maskable Interrupt (XIRQ)
The XIRQ pin provides the capability for applying asynchronous non-maskable interrupts, after
reset initialization, to the MC68HC11G5. During reset, the X-bit in the condition code register is set
and any interrupt is masked until the MCU software enables it. The XIRQ input is level sensitive, and
requires an external pull-up resistor to VDD.
2.2.8
Halt (HALT)
This pin is used as a clean way to force the processor bus into a tri-state condition by means of an
external signal. When HALT is pulled low the processor completes execution of the present
instruction and then tri-states the address and data bus. When the HALT pin is released, the
processor continues normal execution.
The HALT pin can also be used as a “clean way” to put the part into reset. Once pulled into halt,
RESET can be pulled low, ensuring that the processor will be reset on an instruction boundary rather
than in the middle of an instruction.
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Go to: www.freescale.com
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