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參數(shù)資料
| 型號(hào)： | MC68HC11G7CFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁(yè)數(shù)： | 132/195頁(yè) |
| 文件大小： | 1940K |
| 代理商： | MC68HC11G7CFN |
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INPUT/OUTPUT PORTS
4-3
controlled by the DDRA bits whether IC3, IC2, and IC1 are enabled or not. Port A bits 3 – 7 are
controlled by the DDRA bits only when the associated output compare functions are disabled.
Enabling an output compare function forces the corresponding port bit to be an output, irrespective
of the state of the DDRA bit. Using any pins of Port A for timer functions has no effect on the ability
to read these pins as inputs (because input sensing logic is always connected to the port pins).
The OC2, OC3, OC4, and OC5 lines out of Port A are enabled by pairs of control bits in the TCTL1
register. The output compare 1 function is unique in that it allows automatic timer control of any
combination of the five most significant bits of Port A regardless of whether or not they are being
used for another timer function. The OC1 function gains control of Port A bits by setting the
corresponding bits in the OC1M control register. The IC1, IC2, IC3, and IC4 input of Port A are
enabled by pairs of control bits in the TCTL2 register. (See SECTION 6: PROGRAMMABLE
TIMER, REAL TIME INTERRUPT AND PULSE ACCUMULATOR.)
The IC4 function and OC5 function share the same Port A bit and they are selected by the I4/O5
bit in the PACTL register. The pulse accumulator system is enabled, on Port A bit 7 as an input, by
setting the PAEN bit in the PACTL register. Even while the pulse accumulator is enabled, Port A bit
7 may be configured as an output controlled by OC1 or as a general purpose output.
4.4.1
Data Register (PORTA )
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PORTA
$1000
7
6
5
4
3
2
1
0
RESET:
Alternate Pin Function:
and/or:
PA1
OC2
OC3
OC4
OC5/IC4
IC1
IC2
IC3
OC1
—
READ:
Any time (inputs return pin levels; outputs return pin driver input levels).
WRITE:
Data stored in an internal latch. (Drives pins only if configured as outputs.)
RESET:
General purpose high impedance inputs ($00).
Note:
Writes do NOT change pin state when pin is configured for timer output.
4.4.2
Data Direction Register (DDRA )
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
DDRA
$1001
7
6
5
4
3
2
1
0
RESET:
READ:
Any time.
WRITE:
Any time.
RESET:
$00 (all general purpose I/O configured for input only).
0 – Bits set to zero configure the corresponding I/O pins as inputs.
1 – Bits set to one configure the corresponding I/O pins as outputs.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC11K0 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC11K0CFN2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-Bit Microcontroller |
| MC68HC11K0CFN3 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-Bit Microcontroller |
| MC68HC11K0CFN4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC11K0CFNE3 | 功能描述:8位微控制器 -MCU 8B MCU 768 RAM - EPP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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