參數(shù)資料
型號: MC68HC11G7CFN
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84
封裝: PLASTIC, LCC-84
文件頁數(shù): 131/195頁
文件大小: 1940K
代理商: MC68HC11G7CFN
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INPUT/OUTPUT PORTS
4-2
preserve the Port functions that are displaced by the expanded modes, these functions become
externally accessible functions so that they may be emulated with external hardware, if required.
The internal register addresses that become external accesses are PORTB, DDRC, PORTC
and PORTF.
4.2
GENERAL PURPOSE I/O (PORTS A, C, D, G, H, AND J)
As general purpose I/O lines, each pin has associated with it a bit in a PORTx data register and a
bit in the corresponding position in a DDRx register. The data direction register (DDRx) is used to
specify the primary direction of data on the I/O pin. However, specification of a line as an output does
not prevent reading of the line as an input. When a bit configured as an output is read, there are two
kinds of data which may be returned, depending on the internal circuitry of the port. Reading Port
A, Port H, or Port J returns the values sensed at the pins. Reading Port C, Port D, or Port G returns
the values at the inputs to the pin drivers.
When a line is configured as an input by clearing the DDRx bit, the pin becomes a high impedance
input. If a write is executed to a line that is configured as an input, the value will not affect the I/O
pin but the bit will be stored in an internal latch so that, if the line is later reconfigured as an output,
this value will appear at the I/O pin. This operation can be used to preset a value for an output port
prior to configuring it as an output, thereby avoiding glitches on the outputs which may be detrimental
to the operation of the external system.
Ports C, D, and G each have a wired-OR mode of operation which is controlled by the CWOM,
DWOM, and GWOM bits, respectively. If the corresponding xWOM bit is set, the p-channel drivers
in the output buffers are disabled.
Note:
bits 6 and 7 of Port D and bits 4 through 7 of Port J are not implemented.
4.3
FIXED DIRECTION I/O (PORTS B, E, AND F)
The pins for ports B, E, and F have fixed data directions and consequently do not have data direction
registers associated with them. When ports B and F are being used for general purpose I/O, they
are configured as output only ports and reading them returns the levels sensed at the inputs of the
pin drivers. Port E supports the eight A/D channel inputs but these pins may also be used as general
purpose digital inputs. Writing to the Port E address has no meaning or effect.
4.4
PORT A
Port A is an 8-bit bidirectional port. Port A pins can be used as general purpose I/O or for timer
functions. Each pin behaves as a general purpose I/O bit by default, unless a timer function using
that bit is specifically enabled. As general purpose I/O, the data direction of Port A pins are
determined by the corresponding DDRA bits. The directions of Port A bits 0, 1, and 2 are always
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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