INPUT/OUTPUT PORTS
4-5
In the single chip modes (normal and bootstrap), the Port C pins are general purpose I/O pins. Bits
0 – 7 are input or output pins depending on the corresponding bit of DDRC. While a bit is configured
as an output, reading the bit returns the sensed level at the input to the Port C pin driver. At reset,
all DDRC bits are cleared and all Port C bits are configured as inputs.
4.6.1
Data Register (PORTC)
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PORTC
$1006
7
6
5
4
3
2
1
0
RESET:
Alternate Pin Function:
D7
D6
D5
D4
D3
D2
D1
D0
READ:
Any time (inputs return pin level; outputs return pin driver input level).
WRITE:
Data stored in internal latch (drives pins only if configured as outputs)
RESET:
In single chip modes all Port C pins are configured as general purpose inputs.
In expanded modes, Port C is configured as the data bus.
4.6.2
Data Direction Register (DDRC)
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
DDRC
$1007
7
6
5
4
3
2
1
0
RESET:
READ:
Any time.
WRITE:
Any time.
RESET:
$00 (all general purpose I/O configured for input only).
0 – Bits set to zero configure the corresponding I/O pins as inputs.
1 – Bits set to one configure the corresponding I/O pins as outputs.
4.7
PORT D
Port D is a 6-bit bidirectional port which also supports the SCI and SPI systems. When the SCI or
SPI is not needed the associated pins may be used for general purpose I/O.
Port D pins serve several functions depending on the MCU mode and various internal control
registers. If the DWOM bit in the SPCR register is set, the p-channel drivers in the output buffers are
disabled (wired-OR mode).
Port D bit 0 becomes the Receive Data input (RXD) when the SCI receiver is enabled (RE bit in the
SCCR2 register set to one). When the RE bit is clear, Port D bit 0 defaults to being a general purpose
I/O pin controlled by DDRD.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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