RESETS, INTERRUPTS AND LOW POWER MODES
5-7
Table 5-2. Interrupt Vector Masks and Assignments
Vector
Address
Interrupt Source
Masked
by
Priority
(1= High)
FFC0, FFC1
*
FFCA, FFCB
FFCC, FFCD
FFCE, FFCF
Reserved
*
Reserved
Event 2
Event 1
—
I Bit
—
22
21
FFD0, FFD1
FFD2, FFD3
FFD4, FFD5
FFD6, FFD7
Timer Overflow 2
Timer OC7/IC6
Timer OC6/IC5
SCI Serial System
I Bit
18
16
15
24
FFD8, FFD9
FFDA, FFDB
FFDC, FFDD
FFDE, FFDF
SPI Serial Transfer Complete
Pulse Accumulator Input Edge
Pulse Accumulator Overflow
Timer Overflow 1
I Bit
23
20
19
17
FFE0, FFE1
FFE2, FFE3
FFE4, FFE5
FFE6, FFE7
Timer OC5/IC4
Timer Output Compare 4
Timer Output Compare 3
Timer Output Compare 2
I Bit
14
13
12
11
FFE8, FFE9
FFEA, FFEB
FFEC, FFED
FFEE, FFEF
Timer Output Compare 1
Timer Input Capture 3
Timer Input Capture 2
Timer Input Capture 1
I Bit
10
9
8
7
FFFO, FFF1
FFF2, FFF3
FFF4, FFF5
FFF6, FFF7
Real Time Interrupt
SWI
I Bit
X Bit
none
6
5
4
*
FFF8, FFF9
FFFA, FFFB
FFFC, FFFD
FFFE, FFFF
Illegal Opcode Trap
COP Failure (Reset)
COP Clock Fail Monitor (Reset)
none
*
3
2
1
IRQ (external pin)
XIRQ pin ( pseudo NMI)
RESET
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Freescale Semiconductor, Inc.
For More Information On This Product,
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