
Analog-to-Digital Converter (ADC)
Data Sheet
MC68HC908SR12MC68HC08SR12 — Rev. 5.0
236
Analog-to-Digital Converter (ADC)
Freescale Semiconductor
15.4.3 Conversion Time
Conversion starts after a write to the ADSCR. One conversion will take
between 16 and 17 ADC clock cycles, therefore:
The ADC conversion time is determined by the clock source chosen and
the divide ratio selected. The clock source is either the bus clock or
CGMXCLK and is selectable by the ADICLK bit located in the ADC clock
register. The divide ratio is selected by the ADIV[2:0] bits.
For example, if a 4MHz CGMXCLK is selected as the ADC input clock
source, with a divide-by-four prescale, and the bus speed is set at 2MHz:
NOTE:
The ADC frequency must be between f
ADIC
minimum and f
ADIC
maximum to meet ADC specifications. (See
24.12 5.0V ADC Electrical
Characteristics
.)
Since an ADC cycle may comprised of several bus cycles (two in the
previous example) and the start of a conversion is initiated by a bus cycle
write to the ADSCR, from zero to two additional bus cycles may occur
before the start of the initial ADC cycle. This results in a fractional ADC
cycle and is represented as the 17th cycle.
NOTE:
When OPOUT is selected as the ADC input, V
ADIN
, the conversion time
is the accumulation of the op-amp settling time and the normal ADC
conversion time. After writing to the ADSCR to initiate a conversion
cycle, the ADC module sends a signal to the analog module for a
OPOUT output. A signal will be sent back to the ADC by the analog
module to indicate that OPOUT signal is ready for sampling. Upon
receiving this signal, the ADC module starts its normal conversion cycle.
(See
24.12 5.0V ADC Electrical Characteristics
.)
16 to17 ADC cycles
ADC frequency
Conversion time =
Number of bus cycles = conversion time
×
bus frequency
16 to17 ADC cycles
4MHz
÷
4
Conversion time =
Number of bus cycles = 16
μ
s
×
2MHz = 32 to 34 cycles
= 16 to 17
μ
s