
Analog-to-Digital Converter (ADC)
Data Sheet
MC68HC908SR12MC68HC08SR12 — Rev. 5.0
234
Analog-to-Digital Converter (ADC)
Freescale Semiconductor
15.4 Functional Description
The ADC provides thirteen pins for sampling external sources at pins
PTA0/ATD2–PTA5/ATD7, PTC3/ATD8–PTC7/ATD12, and
OPIN1–OPIN2; one internal source from the analog module. An analog
multiplexer allows the single ADC converter to select one of fourteen
ADC channels as ADC voltage in (V
ADIN
). V
ADIN
is converted by the
successive approximation register-based analog-to-digital converter.
When the conversion is completed, ADC places the result in the ADC
data register, high and low byte (ADRH0 and ADRL0), and sets a flag or
generates an interrupt.
An additional three ADC data registers (ADRL1–ADRL3) are available to
store the individual converted data for ADC channels ATD1–ATD3 when
the auto-scan mode is enabled. Data from channel ATD0 is stored in
ADRL0 in the auto-scan mode.
Figure 15-2
shows the structure of the ADC module.
15.4.1 ADC Port I/O Pins
PTA0–PTA5 and PTC3–PTC7 are general-purpose I/O pins that are
shared with the ADC channels, OPIN1 and OPIN2 are two analog inputs
that are always connected to the ADC channel select multiplexer. The
channel select bits, ADCH[4:0], define which ADC channel/port pin will
be used as the input signal. The ADC overrides the port I/O logic by
forcing that pin as input to the ADC. The remaining ADC channels/port
pins are controlled by the port I/O logic and can be used as general-
purpose I/O pins. Writes to the port data register or data direction
register will not have any affect on the port pin that is selected by the
ADC. Read of a port pin which is in use by the ADC will return the pin
condition if the corresponding DDR bit is at logic 0. If the DDR bit is at
logic 1, the value in the port data latch is read.