System Integration Module (SIM)
Data Sheet
MC68HC908SR12MC68HC08SR12 — Rev. 5.0
150
System Integration Module (SIM)
Freescale Semiconductor
9.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is logic 0, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
9.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset. The SIM actively pulls down the RST pin for all internal
reset sources.
9.4.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V
DD
voltage falls to the LVI
TRIPF
voltage. The LVI bit in the SIM reset
status register (SRSR) is set, and the external reset pin (RST) is held low
while the SIM counter counts out 4096 + 32 ICLK cycles. Thirty-two ICLK
cycles later, the CPU is released from reset to allow the reset vector
sequence to occur. The SIM actively pulls down the RST pin for all
internal reset sources.
9.4.2.6 Monitor Mode Entry Module Reset
The monitor mode entry module reset asserts its output to the SIM when
monitor mode is entered in the condition where the reset vectors are
blank ($FF). (See
Section 10. Monitor ROM (MON)
.) When MODRST
gets asserted, an internal reset occurs. The SIM actively pulls down the
RST pin for all internal reset sources.