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| 型號(hào)： | MC68HC08GP8ACFB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 96/126頁(yè) |
| 文件大?。?/td> | 4243K |
| 代理商： | MC68HC08GP8ACFB |
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Computer Operating Properly (COP)
COP Control Register
MC68HC08GP8A
Data Sheet
MOTOROLA
Computer Operating Properly (COP)
71
5.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A
reset vector fetch clears the COP prescaler.
5.3.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the mask
option register. See Section 11. Mask Option Registers (MOR1 and MOR2).
5.3.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the
mask option register. See Section 11. Mask Option Registers (MOR1 and
5.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset
vector. Writing any value to $FFFF clears the COP counter and starts a new
timeout period. Reading location $FFFF returns the low byte of the reset vector.
5.5 Interrupts
The COP does not generate CPU interrupt requests.
5.6 Monitor Mode
When monitor mode is entered with VTST on the IRQ pin, the COP is disabled as
long as VTST remains on the IRQ pin or the RST pin. When monitor mode is
entered by having blank reset vectors and not having VTST on the IRQ pin, the COP
is automatically disabled until a POR occurs.
5.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby
modes.
Address: $FFFF
Bit 7
654
32
1
Bit 0
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
Figure 5-2. COP Control Register (COPCTL)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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