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| 型號(hào)： | MC68HC08GP8ACFB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 81/126頁(yè) |
| 文件大小： | 4243K |
| 代理商： | MC68HC08GP8ACFB |
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Clock Generator Module (CGM)
Data Sheet
MC68HC08GP8A
58
Clock Generator Module (CGM)
MOTOROLA
4.4.8 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the
shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not
represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and amplitude
of CGMXCLK can be unstable at startup.
4.4.9 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which
generates the MCU clocks. CGMOUT is a 50 percent duty cycle clock running at
twice the bus frequency. CGMOUT is software programmable to be either the
oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided
by two.
4.4.10 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
4.5 CGM Registers
These registers control and monitor operation of the CGM:
PLL control register (PCTL)
(See 4.5.1 PLL Control Register.)
PLL bandwidth control register (PBWC)
PLL multiplier select register high (PMSH)
PLL multiplier select register low (PMSL)
PLL VCO range select register (PMRS)
PLL reference divider select register (PMDS)
Figure 4-3 is a summary of the CGM registers.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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