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| 型號(hào)： | MC68HC08GP8ACFB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 85/126頁(yè) |
| 文件大?。?/td> | 4243K |
| 代理商： | MC68HC08GP8ACFB |
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Clock Generator Module (CGM)
CGM Registers
MC68HC08GP8A
Data Sheet
MOTOROLA
Clock Generator Module (CGM)
61
VPR1 and VPR0 — VCO Power-of-Two Range Select Bits
These read/write bits control the VCO’s hardware power-of-two range multiplier
E that, in conjunction with L (See 4.3.3 PLL Circuits, 4.3.6 Programming the
PLL, and 4.5.5 PLL VCO Range Select Register.) controls the hardware
center-of-range frequency, fVRS. VPR1:VPR0 cannot be written when the
PLLON bit is set. Reset clears these bits.
4.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
Selects automatic or manual (software-controlled) bandwidth control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking mode
Table 4-2. PRE1 and PRE0 Programming
PRE1 and PRE0
P
Prescaler Multiplier
00
0
1
01
1
2
10
2
4
11
3
8
Table 4-3. VPR1 and VPR0 Programming
VPR1 and VPR0
E
VCO Power-of-Two
Range Multiplier
00
0
1
01
1
2
10
2
4
11
3(1)
1. Do not program E to a value of 3.
8
Address:
$0037
Bit 7
654321
Bit 0
Read:
AUTO
LOCK
ACQ
0000
R
Write:
Reset:
00000000
= Unimplemented
R
= Reserved
Figure 4-5. PLL Bandwidth Control Register (PBWC)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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