參數(shù)資料
型號(hào)： MC68HC08GP8ACFB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44
封裝： PLASTIC, QFP-44
文件頁數(shù)： 77/126頁
文件大?。?/td> 4243K
代理商： MC68HC08GP8ACFB
Clock Generator Module (CGM)
Data Sheet
MC68HC08GP8A
54
Clock Generator Module (CGM)
MOTOROLA
9.
Calculate and verify the adequacy of the VCO programmed center-of-range
frequency, fVRS. The center-of-range frequency is the midpoint between the
minimum and maximum frequencies attainable by the PLL.
For proper operation,
10.
Verify the choice of P, R, N, E, and L by comparing fVCLK to fVRS and
fVCLKDES. For proper operation, fVCLK must be within the application’s
tolerance of fVCLKDES, and fVRS must be as close as possible to fVCLK.
NOTE:
Exceeding the recommended maximum bus frequency or VCO frequency can
crash the MCU.
11.
Program the PLL registers accordingly:
a.
In the PRE bits of the PLL control register (PCTL), program the binary
equivalent of P.
b.
In the VPR bits of the PLL control register (PCTL), program the binary
equivalent of E.
c.
In the PLL multiplier select register low (PMSL) and the PLL multiplier
select register high (PMSH), program the binary equivalent of N.
d.
In the PLL VCO range select register (PMRS), program the binary
coded equivalent of L.
e.
In the PLL reference divider select register (PMDS), program the
binary coded equivalent of R.
Table 4-1 provides numeric examples (numbers are in hexadecimal notation):
f
VRS
L2
E
×
()f
NOM
=
f
VRS
f
VCLK
–
f
NOM
2
E
×
2
--------------------------
≤
Table 4-1. Numeric Example
fBUS
fRCLK
RN
P
E
L
2.0 MHz
32.768 kHz
1
F5
0
D1
2.4576 MHz
32.768 kHz
1
12C
0
1
80
2.5 MHz
32.768 kHz
1
132
0
1
83
4.0 MHz
32.768 kHz
1
1E9
0
1
D1
4.9152 MHz
32.768 kHz
1
258
0
2
80
5.0 MHz
32.768 kHz
1
263
0
2
82
7.3728 MHz
32.768 kHz
1
384
0
2
C0
8.0 MHz
32.768 kHz
1
3D1
0
2
D0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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