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| 型號(hào)： | MC68HC08GP8ACFB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 5/126頁(yè) |
| 文件大?。?/td> | 4243K |
| 代理商： | MC68HC08GP8ACFB |
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Low-Power Modes
Data Sheet
MC68HC08GP8A
102
Low-Power Modes
MOTOROLA
9.3 Break Module (BRK)
9.3.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine, the user
can subtract one from the return address on the stack if the SBSW bit in the break
status register is set.
9.3.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect
break module register states.
9.4 Central Processor Unit (CPU)
9.4.1 Wait Mode
The WAIT instruction:
Clears the interrupt mask (I bit) in the condition code register, enabling
interrupts. After exit from wait mode by interrupt, the I bit remains clear. After
exit by reset, the I bit is set.
Disables the CPU clock
9.4.2 Stop Mode
The STOP instruction:
Clears the interrupt mask (I bit) in the condition code register, enabling
external interrupts. After exit from stop mode by external interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
9.5 Clock Generator Module (CGM)
9.5.1 Wait Mode
The CGM remains active in wait mode. Before entering wait mode, software can
disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL
control register (PCTL). Less power-sensitive applications can disengage the PLL
without turning it off. Applications that require the PLL to wake the MCU from wait
mode also can deselect the PLL output without turning off the PLL.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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