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參數(shù)資料
| 型號： | MC68HC08GP8ACFB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 101/126頁 |
| 文件大?。?/td> | 4243K |
| 代理商： | MC68HC08GP8ACFB |
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Central Processor Unit (CPU)
Data Sheet
MC68HC08GP8A
76
Central Processor Unit (CPU)
MOTOROLA
6.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next
instruction or operand to be fetched.
Normally, the program counter automatically increments to the next sequential
memory location every time an instruction or operand is fetched. Jump, branch,
and interrupt operations load the program counter with an address other than that
of the next sequential location.
During reset, the program counter is loaded with the reset vector address located
at $FFFE and $FFFF. The vector address is the address of the first instruction to
be executed after exiting the reset state.
6.3.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five flags that
indicate the results of the instruction just executed. Bits 6 and 5 are set
permanently to logic 1. The following paragraphs describe the functions of the
condition code register.
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The
signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
Bit
15
14
13
12
11
10
987654321
Bit
0
Read:
Write:
Reset:
Loaded with vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
Bit 7
654321
Bit 0
Read:
V1
1
H
I
N
Z
C
Write:
Reset:
X1
1X1X
X
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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