參數(shù)資料
型號(hào)： MC68HC08GP8ACFB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44
封裝： PLASTIC, QFP-44
文件頁數(shù)： 10/126頁
文件大?。?/td> 4243K
代理商： MC68HC08GP8ACFB
Low-Power Modes
Exiting Stop Mode
MC68HC08GP8A
Data Sheet
MOTOROLA
Low-Power Modes
107
Serial peripheral interface module (SPI) interrupt — A CPU interrupt request
from the SPI loads the program counter with the contents of:
–
$FFE8 and $FFE9; SPI transmitter
–
$FFEA and $FFEB; SPI receiver
Serial communications interface module (SCI) interrupt — A CPU interrupt
request from the SCI loads the program counter with the contents of:
–
$FFE2 and $FFE3; SCI transmitter
–
$FFE4 and $FFE5; SCI receiver
–
$FFE6 and $FFE7; SCI receiver error
Analog-to-digital converter module (ADC) interrupt — A CPU interrupt
request from the ADC loads the program counter with the contents of:
$FFDE and $FFDF; ADC conversion complete.
Timebase module (TBM) interrupt — A CPU interrupt request from the TBM
loads the program counter with the contents of: $FFDC and $FFDD; TBM
interrupt.
9.15 Exiting Stop Mode
These events restart the system clocks and load the program counter with the reset
vector or with an interrupt vector:
External reset — A logic 0 on the RST pin resets the MCU and loads the
program counter with the contents of locations $FFFE and $FFFF.
External interrupt — A high-to-low transition on an external interrupt pin
loads the program counter with the contents of locations:
–
$FFFA and $FFFB; IRQ pin
–
$FFE0 and $FFE1; keyboard interrupt pins
Low-voltage inhibit (LVI) reset — A power supply voltage below the LVItripf
voltage resets the MCU and loads the program counter with the contents of
locations $FFFE and $FFFF.
Timebase module (TBM) interrupt — When the OSCSTOPENB bit in the
MOR2 register is set, a TBM interrupt loads the program counter with the
contents of locations $FFDC and $FFDD when the timebase counter has
rolled over. This allows the TBM to generate a periodic wakeup from stop
mode.
Upon exit from stop mode, the system clocks begin running after an oscillator
stabilization delay. A 12-bit stop recovery counter inhibits the system clocks for
4096 CGMXCLK cycles after the reset or external interrupt.
The short stop recovery bit, SSREC, in the MOR register controls the oscillator
stabilization delay during stop recovery. Setting SSREC reduces stop recovery
time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles.
NOTE:
Use the full stop recovery time (SSREC = 0) in applications that use an external
crystal.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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