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參數(shù)資料
| 型號： | MC68HC08GP8ACFB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 69/126頁 |
| 文件大?。?/td> | 4243K |
| 代理商： | MC68HC08GP8ACFB |
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MC68HC08GP8A
Data Sheet
MOTOROLA
Clock Generator Module (CGM)
47
Data Sheet — MC68HC08GP8A
Section 4. Clock Generator Module (CGM)
4.1 Introduction
This section describes the clock generator module. The CGM generates the crystal
clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM
also generates the base clock signal, CGMOUT, which is based on either the
crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK,
divided by two. In user mode, CGMOUT is the clock from which the SIM derives
the system clocks, including the bus clock, which is at a frequency of CGMOUT/2.
In monitor mode, PTC3 determines the bus clock. The PLL is a fully functional
frequency generator designed for use with crystals or ceramic resonators. The PLL
can generate an 8-MHz bus frequency using a 32-kHz crystal.
4.2 Features
Features of the CGM include:
Phase-locked loop with output frequency in integer multiples of an integer
dividend of the crystal reference
Low-frequency crystal operation with low-power operation and high-output
frequency resolution
Programmable prescaler for power-of-two increases in frequency
Programmable hardware voltage-controlled oscillator (VCO) for low-jitter
operation
Automatic bandwidth control mode for low-jitter operation
Automatic frequency lock detector
CPU interrupt on entry or exit from locked condition
Mask option register bit to allow oscillator operation during stop mode
4.3 Functional Description
The CGM consists of three major submodules:
Crystal oscillator circuit — The crystal oscillator circuit generates the
constant crystal frequency clock, CGMXCLK.
Phase-locked loop (PLL) — The PLL generates the programmable VCO
frequency clock, CGMVCLK.
Base clock selector circuit — This software-controlled circuit selects either
CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as
the base clock, CGMOUT. The SIM derives the system clocks from either
CGMOUT or CGMXCLK.
Figure 4-1 shows the structure of the CGM.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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